CHIPS Alliance

All

109 repositories

Caliptra
Public
Caliptra IP and firmware for integrated Root of Trust block
Apache License 2.0
•33•233•17•2•Updated Nov 7, 2024Nov 7, 2024
caliptra-sw
Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
Rust
•
Apache License 2.0
•44•94•100•58•Updated Nov 7, 2024Nov 7, 2024
Surelog
Public
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi
C++
•
Apache License 2.0
•69•362•51•0•Updated Nov 7, 2024Nov 7, 2024
Cores-VeeR-EL2
Public
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital
SystemVerilog
•
Apache License 2.0
•75•252•25•10•Updated Nov 7, 2024Nov 7, 2024
i3c-core
Public
SystemVerilog
•
Apache License 2.0
•3•6•1•1•Updated Nov 7, 2024Nov 7, 2024
t1
Public
Scala
•
Apache License 2.0
•23•118•16•23•Updated Nov 7, 2024Nov 7, 2024
synlig-logs
Public
SystemVerilog
•0•0•0•0•Updated Nov 7, 2024Nov 7, 2024
synlig
Public
SystemVerilog synthesis tool
Verilog
•
Apache License 2.0
•21•168•65•8•Updated Nov 7, 2024Nov 7, 2024
sv-tests-results
Public
Output of the sv-tests runs.
HTML
•1•5•0•0•Updated Nov 7, 2024Nov 7, 2024
caliptra-rtl
Public
HW Design Collateral for Caliptra RoT IP
SystemVerilog
•
Apache License 2.0
•37•75•68•10•Updated Nov 7, 2024Nov 7, 2024
sv-tests
Public
Test suite designed to check compliance with the SystemVerilog standard.
rtl verilog systemverilog hdl compliance-testing symbiflow
SystemVerilog
•
ISC License
•75•295•45•21•Updated Nov 7, 2024Nov 7, 2024
chisel
Public
Chisel: A Modern Hardware Design Language
chip-generator chisel rtl chisel3 firrtl scala verilog
Scala
•
Apache License 2.0
•597•4k•313•169•Updated Nov 6, 2024Nov 6, 2024
adams-bridge
Public
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
cryptography digital-signature lattice pqc ml-dsa-87
SystemVerilog
•
Apache License 2.0
•1•8•0•0•Updated Nov 6, 2024Nov 6, 2024
rocket-chip-fpga-shells
Public
Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
Scala
•
Apache License 2.0
•21•16•1•1•Updated Nov 6, 2024Nov 6, 2024
caliptra-ss
Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
security rot ocp root-of-trust caliptra opencomputeproject
SystemVerilog
•
Apache License 2.0
•2•7•11•1•Updated Nov 5, 2024Nov 5, 2024
firtool-resolver
Public
Scala
•1•1•0•1•Updated Nov 5, 2024Nov 5, 2024
rocket-uncore
Public
Scala
•0•6•0•3•Updated Nov 4, 2024Nov 4, 2024
rvdecoderdb
Public
The Scala parser to parse riscv/riscv-opcodes generate
Scala
•0•9•0•1•Updated Nov 4, 2024Nov 4, 2024
systolic
Public
A matrix multiplication implementation via systolic array
Nix
•0•1•0•1•Updated Nov 3, 2024Nov 3, 2024
firrtl-spec
Public
The specification for the FIRRTL language
TeX
•28•45•22•18•Updated Nov 1, 2024Nov 1, 2024
chisel-nix
Public
Nix template for the chisel-based industrial designing flows.
Nix
•1•28•0•0•Updated Nov 1, 2024Nov 1, 2024
caliptra-dpe
Public
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
Rust
•
Apache License 2.0
•22•16•12•6•Updated Nov 1, 2024Nov 1, 2024
rocket-pcb
Public
PCB libraries and templates for rocket-chip based FPGA/ASIC designs
Verilog
•
Apache License 2.0
•2•7•0•1•Updated Nov 1, 2024Nov 1, 2024
rocket-pcblib
Public
Apache License 2.0
•0•1•0•0•Updated Nov 1, 2024Nov 1, 2024
rocket-chip
Public
Rocket Chip Generator
chisel scala rocket-chip chip-generator riscv rtl
Scala
•
Other
•1.1k•3.3k•227•62•Updated Oct 30, 2024Oct 30, 2024
chips-alliance-website
Public
SCSS
•
MIT License
•3•3•9•8•Updated Oct 24, 2024Oct 24, 2024
verible-linter-action
Public
Automatic SystemVerilog linting in github actions with the help of Verible
Python
•
Apache License 2.0
•13•27•2•0•Updated Oct 23, 2024Oct 23, 2024
riscv-vector-tests
Public
Unit tests generator for RVV 1.0
generator spike riscv testsuite rvv
Go
•
Apache License 2.0
•19•59•4•1•Updated Oct 19, 2024Oct 19, 2024
verible
Public
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
productivity analysis style-linter language-server-protocol syntax-tree lexer yacc systemverilog hacktoberfest lsp-server
C++
•
Other
•212•1.4k•473•25•Updated Oct 16, 2024Oct 16, 2024
f4pga
Public
FOSS Flow For FPGA
documentation sphinx symbiflow
Python
•
Apache License 2.0
•48•359•13•13•Updated Oct 15, 2024Oct 15, 2024