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Pull requests: chipsalliance/caliptra-rtl

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Pull requests list

Increased mbox size to 256KB
#681 opened Jan 4, 2025 by Nitsirks Loading…
Make WDT more module for MCI reuse
#679 opened Jan 3, 2025 by clayton8 Loading…
12
Publish HTML docs for 1.1 RTL in addition to main
#676 opened Dec 23, 2024 by jhand2 Loading…
3
Updates to caliptra-rtl required by fuse_controller
#673 opened Dec 19, 2024 by anjpar Loading…
mldsa pcr signing
#670 opened Dec 19, 2024 by mojtaba-bisheh Loading…
1
@mojtaba-bisheh
2
[RDL] Reduce fuse_key_manifest_pk_hash_mask back to 4-bit reg
#669 opened Dec 19, 2024 by calebofearth Loading…
Update vendored OpenTitan entropy IPs to Earlgrey-PROD-M5
#665 opened Dec 16, 2024 by nbdd0121 Loading…
2
[DOCS] Document some paranoia checks in release checklist
#656 opened Dec 6, 2024 by calebofearth • Draft
DELETE THIS -- TEST PR -- User/anjpar/caliptra ss fuse ctrl
#607 opened Oct 23, 2024 by nileshbpat • Draft
1
Add coverage report
#587 opened Sep 10, 2024 by kiryk Loading…
2
Integration doc - use RTL signal names
#570 opened Aug 14, 2024 by steven-bellock Loading…
4
Integration docs: Add recommended TRNG self-test thresholds.
#569 opened Aug 13, 2024 by korran Loading…
Add test for JTAG during uC reset
#554 opened Jul 4, 2024 by robertszczepanski Loading…
Patch 1.0 RTL with Lint Fixes enhancement New feature or request
#518 opened May 17, 2024 by calebofearth Loading…
@calebofearth
9
libs: ahb_slv_sif: Latch hsize on address phase Future
#502 opened Apr 17, 2024 by wkkuna Loading…
3
Fix PC setup after waking from clock gating in Verilator Future
#380 opened Jan 16, 2024 by robertszczepanski Loading…
12
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