Clarify interaction of CBOs and PBMTs

This is the suggestion from riscv/riscv-CMOs#57 (comment) which was never applied.

The behaviour can be technically inferred from this paragraph - as noted in one of the comments on that issue:

> Accessing the same location using different cacheability attributes may cause loss of coherence. Executing the following sequence between such accesses prevents both loss of coherence and loss of memory ordering: `fence iorw, iorw`, followed by `cbo.flush` to an address of that location, followed by a `fence iorw, iorw`.

However this is subtle, which means implementation bugs are likely. Making it explicit removes the risk of confusion and the resulting bugs.

src/cmo.adoc

@@ -779,6 +779,13 @@ The following instructions comprise the Zicbom extension:
 
 |===
 
+[NOTE]
+====
+_Cache-block management instructions operate on the cache block independently
+of whether Page-Based Memory Types (PBMT) downgrade the memory attribute
+to non-cacheable._
+====
+
 [#Zicboz,reftext="Cache-Block Zero Instructions"]
 ==== Cache-Block Zero Instructions