Skip to content

Issues: riscv/riscv-isa-manual

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

203 Open 696 Closed
203 Open 696 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Sscofpmf spec says it is written as a diff
#1732 opened Nov 20, 2024 by Timmmm
1
Question and Bug about "Atomicity Axiom Rule" in RVWMO Explanatory Material, Version 0.1
#1731 opened Nov 19, 2024 by diantaowang
1
Specify what imprecise traps are
#1728 opened Nov 15, 2024 by Timmmm
5
Conflicting exception types caused by misaligned AMO instructions.
#1726 opened Nov 15, 2024 by jillleon007
3
Bus-error clarification
#1725 opened Nov 14, 2024 by oolegoon
2
How to decide the memory attribute when PBMT=NC & PMA=IO ?
#1723 opened Nov 13, 2024 by rock-ifly
1
How to understand this sentence in the PM spec--"Alternatively, an implementation may choose to "waste" TLB capacity by having up to 4 duplicate entries for each page."
#1721 opened Nov 11, 2024 by chara811
1
When PMLEN=16 and hgatp=sv48x4, Is GPA[49:48] =2b00?
#1720 opened Nov 11, 2024 by chara811
1
Can index-ordered and index-unordered VL*/VS* instructions be used to access device address space?
#1719 opened Nov 9, 2024 by Steven-Li-Xiaogang
1
Sail Manual link is 404
#1718 opened Nov 8, 2024 by ha0lyu
1
Reason for vstart≥vl requiring undisturbed tail elements even with ta vtype
#1715 opened Nov 7, 2024 by dzaima
1
Specify misa.M behaviour with Zmmul
#1711 opened Nov 5, 2024 by Timmmm
3
"In a two-stage address translation, is it possible to configure VSatp as sv39 and hgatp as sv48, or VSatp as sv48 and hgatp as sv39?
#1703 opened Oct 31, 2024 by chara811
1
When the PM feature is enabled, can PMLEN be set to 7 in sv48 mode?
#1702 opened Oct 30, 2024 by chara811
4
Please extend the explanation on slideup/slidedown
#1701 opened Oct 29, 2024 by lu-zero
What are the sources of memory attributes under different translation mechanisms?
#1699 opened Oct 28, 2024 by chara811
4
why are the hstatus.VTSR/VTVM and VTW permission check different?
#1695 opened Oct 23, 2024 by yinhanquan
Hypervisor chapter uses term HSLEN but I think it means HSXLEN
#1693 opened Oct 22, 2024 by james-ball-qualcomm
2
how to understand the PMA and the PBMT?
#1687 opened Oct 17, 2024 by rock-ifly
23
Possibility of 'Environment call from S-mode' delegation to S-mode
#1673 opened Oct 4, 2024 by evgeniy-paltsev
1
"...will be furninshed by the forthcoming extension" comments need to be removed Good First Issue This label indicates an issue that is well suited for a new contributor to tackle.
#1672 opened Oct 4, 2024 by Timmmm
Remove J extension placeholder chapter
#1668 opened Oct 3, 2024 by wmat
1
Help wanted: WARL and WLRL definitions help wanted
#1655 opened Sep 26, 2024 by kersten1
question about vstart
#1641 opened Sep 19, 2024 by ddxoxpp
Add instruction names
#1638 opened Sep 16, 2024 by ThinkOpenly
3
ProTip! Follow long discussions with comments:>50.