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    56 repositories

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •304•699•25•25•Updated Nov 20, 2024Nov 20, 2024

    • riscv-cfi

      Public
      This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •21•85•1•0•Updated Nov 20, 2024Nov 20, 2024

    • riscv-zalasr

      Public
      The ISA specification for the Zalasr extension.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •1•1•3•0•Updated Nov 18, 2024Nov 18, 2024

    • guides

      Public
      RISC-V International Guides
      Creative Commons Zero v1.0 Universal
      •0•0•0•0•Updated Nov 18, 2024Nov 18, 2024

    • riscv-docs-base-container-image

      Public
      A base container image populated with the dependencies to build the RISC-V Documentation.
      Apache License 2.0
      •8•9•0•4•Updated Nov 18, 2024Nov 18, 2024

    • riscv-zilsd

      Public
      Zilsd (Load/Store Pair for RV32) Fast-Track Extension
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •3•7•5•1•Updated Nov 15, 2024Nov 15, 2024

    • docs-dev-guide

      Public
      Documentation developer guide
      TeX
      •
      Creative Commons Attribution 4.0 International
      •30•89•4•1•Updated Nov 15, 2024Nov 15, 2024

    • riscv-aia

      Public
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •19•81•25•0•Updated Nov 15, 2024Nov 15, 2024

    • riscv-isa-manual

      Public
      RISC-V Instruction Set Manual
      TeX
      •
      Creative Commons Attribution 4.0 International
      •643•3.7k•203•15•Updated Nov 14, 2024Nov 14, 2024

    • riscv-smmtt

      Public
      This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
      access-controltrusted-computingtrusted-execution-environmentconfidential-computingsmmttsupervisor-domainsap-tee
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •16•42•0•1•Updated Nov 14, 2024Nov 14, 2024

    • riscv-cheri

      Public
      This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
      memory-safetycapabilitiescompartmentalization
      Python
      •
      Creative Commons Attribution 4.0 International
      •29•55•32•5•Updated Nov 13, 2024Nov 13, 2024

    • sail-riscv

      Public
      Sail RISC-V model
      Coq
      •
      Other
      •168•462•90•62•Updated Nov 13, 2024Nov 13, 2024

    • learn

      Public
      Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
      Creative Commons Zero v1.0 Universal
      •68•571•0•0•Updated Nov 13, 2024Nov 13, 2024

    • riscv-fast-interrupt

      Public
      Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •49•247•40•3•Updated Nov 11, 2024Nov 11, 2024

    • riscv-performance-events

      Public
      RISC-V Performance Events Specification
      Python
      •
      Creative Commons Attribution 4.0 International
      •2•4•5•1•Updated Nov 6, 2024Nov 6, 2024

    • docs-spec-template

      Public template
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •19•21•2•1•Updated Nov 6, 2024Nov 6, 2024

    • meta-riscv

      Public
      OpenEmbedded/Yocto layer for RISC-V Architecture
      riscvyocto-layeryoctoopenembeddedyocto-metaopenembedded-layerrisc-v
      BitBake
      •
      Other
      •140•366•17•3•Updated Nov 4, 2024Nov 4, 2024

    • riscv-memory-tagging

      Public
      Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •2•7•4•1•Updated Nov 1, 2024Nov 1, 2024

    • self-hosted-trace

      Public
      RISC-V Self-hosted Trace Development Repositoty
      TeX
      •
      Creative Commons Attribution 4.0 International
      •643•0•0•0•Updated Oct 30, 2024Oct 30, 2024

    • configuration-structure

      Public
      RISC-V Configuration Structure
      Python
      •
      Creative Commons Attribution 4.0 International
      •17•37•14•1•Updated Oct 30, 2024Oct 30, 2024

    • riscv-profiles

      Public
      RISC-V Architecture Profiles
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •33•119•10•1•Updated Oct 28, 2024Oct 28, 2024

    • riscv-control-transfer-records

      Public
      This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•17•0•0•Updated Oct 24, 2024Oct 24, 2024

    • riscv-j-extension

      Public
      Working Draft of the RISC-V J Extension Specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •17•169•7•3•Updated Oct 16, 2024Oct 16, 2024

    • docs-resources

      Public
      Creative Commons Attribution 4.0 International
      •15•27•3•2•Updated Oct 1, 2024Oct 1, 2024

    • integrated-matrix-extension

      Public
      RISC-V Integrated Matrix Development Repository
      TeX
      •
      Creative Commons Attribution 4.0 International
      •643•5•0•0•Updated Sep 30, 2024Sep 30, 2024

    • ft-trigger-delegation

      Public
      Trigger Delegation Fast-Track Specification
      TeX
      •
      Creative Commons Attribution 4.0 International
      •643•0•0•1•Updated Sep 26, 2024Sep 26, 2024

    • riscv-debug-spec

      Public
      Working Draft of the RISC-V Debug Specification Standard
      Python
      •
      Other
      •92•459•55•7•Updated Sep 12, 2024Sep 12, 2024

    • riscv-spmp

      Public
      The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.
      TeX
      •
      Creative Commons Attribution 4.0 International
      •7•11•2•1•Updated Sep 10, 2024Sep 10, 2024

    • riscv-glossary

      Public
      Makefile
      •5•5•10•1•Updated Sep 5, 2024Sep 5, 2024

    • riscv-double-trap

      Public
      RISC-V Double Trap Fast-Track Extension
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •3•12•0•0•Updated Aug 23, 2024Aug 23, 2024