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34 Open 229 Closed
34 Open 229 Closed
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Issues list

Scratch Swap CSR (sscratchcswl) CSR section missing in ssclic chapter
#422 opened Sep 30, 2024 by james-ball-qualcomm
The smclicshv extension naming (i.e. sm*) suggests it only has M-mode features but it affects S-mode and has one S-mode CSR bit
#421 opened Sep 30, 2024 by james-ball-qualcomm
Recommend moving definition of indirect CSRs into their own chapter and clarifying they are accessed via M-mode or S-mode CSRs.
#420 opened Sep 30, 2024 by james-ball-qualcomm
@dansmathers @christian-herber-nxp
@james-ball-qualcomm @jb-brelot-nxp
1
Inconsistency on which fields are zeroed when switching to CLINT mode
#418 opened Sep 24, 2024 by Timmmm
Simplify and fully specify xscratchcsw[l]
#416 opened Sep 23, 2024 by Timmmm
Write side-effects for csrrs rd, mnxti, rs1 when rs1 is not x0
#415 opened Sep 18, 2024 by MarkHillCodasip
1
Move register layout definitions into wavedrom
#414 opened Sep 17, 2024 by christian-herber-nxp
@wmat
5
Make Ssclic mandatory if smclic is implemented and S mode is implemented.
#413 opened Sep 16, 2024 by jb-brelot-nxp
2
Explicitly list dependence on Smcsrind/Sscsrind
#412 opened Sep 12, 2024 by christian-herber-nxp
Smclic section contains a lot of changes relevant only to S-mode
#409 opened Sep 11, 2024 by christian-herber-nxp
8
The text definition of xscratchcswl is incomplete
#407 opened Sep 11, 2024 by Timmmm
1
xscratchcswl privilege behaviour not fully specified
#406 opened Sep 11, 2024 by Timmmm
1
Clarify behaviour of xnxti register version in smclicshv
#402 opened Aug 27, 2024 by jakubahh
Make shv a per level property
#400 opened Aug 15, 2024 by christian-herber-nxp
1
an exception trap on the trap handler function address fetch cannot return to the instruction interrupted (smclicshv)
#399 opened Jul 15, 2024 by hirooih
Questions on Release 0.9
#398 opened Jul 15, 2024 by hirooih
Missing a catchy terminology for the selection priority
#396 opened May 16, 2024 by christian-herber-nxp
6
Require immediate evaluation of clicintie and clicintip
#378 opened Mar 5, 2024 by Silabs-ArjanB
11
How should non-normative text be specified in CLIC spec v1.0 resolve for 1.0
#376 opened Mar 5, 2024 by christian-herber-nxp
5
xcause.inhv conflicts with enabling CLIC per mode post-v1.0 To be handled after v1.0
#348 opened Aug 18, 2023 by JamesKenneyImperas
2
Add optional support for hardware register save e.g. shadow register sets? post-v1.0 To be handled after v1.0
#329 opened Apr 23, 2023 by brucehoult
3
Hypervisor mode should be discussed. post-v1.0 To be handled after v1.0
#248 opened Jun 21, 2022 by kasanovic
2
is spike support required? post-v1.0 To be handled after v1.0
#242 opened May 24, 2022 by dansmathers
4
Allow mix of CLIC/CLINT at different privilege modes post-v1.0 To be handled after v1.0
#192 opened Jan 18, 2022 by kasanovic
QEMU updates post-v1.0 To be handled after v1.0
#187 opened Dec 21, 2021 by dansmathers
1
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