[rtl] vrf report ready need free record.

chipsalliance · Jan 25, 2024 · e5ad358 · e5ad358
1 parent a53a7e5
commit e5ad358
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Showing 2 changed files with 4 additions and 3 deletions.
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -958,12 +958,13 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
 
 
   val slotEnqueueFire: Seq[Bool] = Seq.tabulate(parameter.chainingSize) { slotIndex =>
-    val enqueueReady: Bool = !slotOccupied(slotIndex)
+    val enqueueReady: Bool = Wire(Bool())
     val enqueueValid: Bool = Wire(Bool())
     val enqueueFire: Bool = enqueueReady && enqueueValid
     // enqueue from lane request
     if (slotIndex == parameter.chainingSize - 1) {
       enqueueValid := laneRequest.valid
+      enqueueReady := !slotOccupied(slotIndex) && vrf.instructionWriteReport.ready
       when(enqueueFire) {
         slotControl(slotIndex) := entranceControl
         maskGroupCountVec(slotIndex) := 0.U(parameter.maskGroupSizeBits.W)
@@ -974,6 +975,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     } else {
       // shifter for slot
       enqueueValid := slotCanShift(slotIndex + 1) && slotOccupied(slotIndex + 1)
+      enqueueReady := !slotOccupied(slotIndex)
       when(enqueueFire) {
         slotControl(slotIndex) := slotControl(slotIndex + 1)
         maskGroupCountVec(slotIndex) := maskGroupCountVec(slotIndex + 1)

diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala
@@ -243,8 +243,7 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
   val recordFFO:  UInt = ffo(freeRecord)
   val recordEnq:  UInt = Wire(UInt((parameter.chainingSize + 1).W))
   // handle VRF hazard
-  // TODO: move to [[V]]
-  instructionWriteReport.ready := true.B
+  instructionWriteReport.ready := freeRecord.orR
   recordEnq := Mux(
     // 纯粹的lsu指令的记录不需要ready
     instructionWriteReport.valid,