[rtl] lastGroupForInstruction was calculated incorrectly.

chipsalliance · Jan 25, 2024 · a53a7e5 · a53a7e5
1 parent dd91512
commit a53a7e5
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Showing 2 changed files with 4 additions and 5 deletions.
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -873,9 +873,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     // vl is too small, don't need to use this lane.
     (((laneIndex ## 0.U(2.W)) >> csrInterface.vSew).asUInt >= csrInterface.vl || maskLogicCompleted) &&
       // for 'nr' type instructions, they will need another complete signal.
-      !laneRequest.bits.decodeResult(Decoder.nr) &&
-      // complete is notified by LSU.
-      !laneRequest.bits.loadStore
+      !laneRequest.bits.decodeResult(Decoder.nr)
   // indicate if this is the mask type.
   entranceControl.mask.valid := laneRequest.bits.mask
   // assign mask from [[V]]
@@ -886,7 +884,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   entranceControl.vrfWriteMask := 0.U
 
   // calculate last group
-  val lastElementIndex: UInt = (csrInterface.vl - 1.U)(parameter.vlMaxBits - 2, 0)
+  val lastElementIndex: UInt = (csrInterface.vl - csrInterface.vl.orR)(parameter.vlMaxBits - 2, 0)
   val requestVSew1H:    UInt = UIntToOH(csrInterface.vSew)
 
   /** For an instruction, the last group is not executed by all lanes,

diff --git a/t1/src/lsu/SimpleAccessUnit.scala b/t1/src/lsu/SimpleAccessUnit.scala
@@ -333,7 +333,8 @@ class SimpleAccessUnit(param: MSHRParam) extends Module  with LSUPublic {
     case (offset, index) =>
       // offsetReadResult(index).valid: new offset came
       // (offset.valid && !usedIndexedInstructionOffsets(index)): old unused offset
-      offset.valid := offsetReadResult(index).valid || (offset.valid && !usedIndexedInstructionOffsets(index))
+      offset.valid := offsetReadResult(index).valid ||
+        (offset.valid && !usedIndexedInstructionOffsets(index) && !status.last)
       // select from new and old.
       offset.bits := Mux(offsetReadResult(index).valid, offsetReadResult(index).bits, offset.bits)
   }