[t1rocket] fix scalar float reg write queue check

chipsalliance · Aug 25, 2024 · ad1086b · ad1086b
1 parent e8c51b7
commit ad1086b
Showing 1 changed file with 5 additions and 5 deletions.
diff --git a/t1rocketemu/test_common/src/spike_runner.rs b/t1rocketemu/test_common/src/spike_runner.rs
@@ -25,10 +25,10 @@ pub struct SpikeRunner {
   /// dependency, the vector instruction should be issued in order.
   pub vector_queue: VecDeque<SpikeEvent>,
 
-  /// scalar queue to arrange the order of scalar reg / freg write instructions
+  /// scalar queue to arrange the order of scalar reg write instructions
   pub scalar_queue: VecDeque<SpikeEvent>,
 
-  /// scalar queue to arrange the order of scalar reg / freg write instructions
+  /// float queue to arrange the order of scalar freg write instructions
   pub float_queue: VecDeque<SpikeEvent>,
 
   /// config for v extension
@@ -142,7 +142,7 @@ impl SpikeRunner {
         let se = self.spike_step();
         if se.is_scalar() && se.is_rd_written {
           return se;
-        } else if se.is_fd_written {
+        } else if se.is_scalar() && se.is_fd_written {
           self.float_queue.push_front(se.clone());
         } else if se.is_v() {
           self.vector_queue.push_front(se.clone());
@@ -161,7 +161,7 @@ impl SpikeRunner {
         let se = self.spike_step();
         if se.is_scalar() && se.is_rd_written {
           self.scalar_queue.push_front(se.clone());
-        } else if se.is_fd_written {
+        } else if se.is_scalar() && se.is_fd_written {
           return se;
         } else if se.is_v() {
           self.vector_queue.push_front(se.clone());
@@ -180,7 +180,7 @@ impl SpikeRunner {
         let se = self.spike_step();
         if se.is_scalar() && se.is_rd_written {
           self.scalar_queue.push_front(se.clone());
-        } else if se.is_fd_written {
+        } else if se.is_scalar() && se.is_fd_written {
           self.float_queue.push_front(se.clone());
         } else if se.is_v() {
           return se;