[rocketv] fix vcsr write.

chipsalliance · Aug 25, 2024 · e8c51b7 · e8c51b7
1 parent bd8099d
commit e8c51b7
Showing 1 changed file with 6 additions and 1 deletion.
diff --git a/rocketv/src/CSR.scala b/rocketv/src/CSR.scala
@@ -658,7 +658,8 @@ class CSR(val parameter: CSRParameter)
   val reg_wfi = withClock(io.ungatedClock) { RegInit(false.B) }
 
   val reg_fflags = Reg(UInt(5.W))
-  val reg_frm = Reg(UInt(3.W))
+  // todo: need init?
+  val reg_frm = RegInit(0.U(3.W))
 
   val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W))
   io.inhibitCycle := reg_mcountinhibit(0)
@@ -1741,6 +1742,10 @@ class CSR(val parameter: CSRParameter)
       when(decoded_addr(CSRs.vxrm)) {
         vector.get.states("vxrm") := wdata
       }
+      when(decoded_addr(CSRs.vcsr)) {
+        vector.get.states("vxrm") := wdata(2, 1)
+        vector.get.states("vxsat") := wdata(0)
+      }
     }
   } else {
     setVlReadData := 0.U