[rtl] fix v0 write token.

chipsalliance · Nov 15, 2024 · a80387b · a80387b
1 parent 76530e0
commit a80387b
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Showing 2 changed files with 13 additions and 2 deletions.
diff --git a/t1/src/T1.scala b/t1/src/T1.scala
@@ -927,6 +927,10 @@ class T1(val parameter: T1Parameter)
   tokenManager.instructionIssue.bits.useV0AsMask      := maskType
   tokenManager.instructionIssue.bits.isLoadStore      := !requestRegDequeue.bits.instruction(6)
   tokenManager.instructionIssue.bits.toLane           := !noOffsetReadLoadStore && !maskUnitInstruction
+  tokenManager.lsuWriteV0.zip(lsu.vrfWritePort).foreach { case (token, write) =>
+    token.valid := write.fire && write.bits.vd === 0.U && write.bits.mask.orR
+    token.bits := write.bits.instructionIndex
+  }
 
   // instruction commit
   {

diff --git a/t1/src/sequencer/T1TokenManager.scala b/t1/src/sequencer/T1TokenManager.scala
@@ -20,6 +20,9 @@ class T1TokenManager(parameter: T1Parameter) extends Module {
   @public
   val instructionIssue: ValidIO[IssueToken] = IO(Flipped(Valid(new IssueToken(parameter))))
 
+  @public
+  val lsuWriteV0: Vec[ValidIO[UInt]] = IO(Vec(parameter.laneNumber, Flipped(Valid(UInt(parameter.instructionIndexBits.W)))))
+
   @public
   val issueAllow: Bool = IO(Output(Bool()))
 
@@ -44,10 +47,14 @@ class T1TokenManager(parameter: T1Parameter) extends Module {
 
   // v0 write token
   val v0WriteValidVec: Seq[UInt] = Seq.tabulate(parameter.laneNumber) { laneIndex =>
-    val v0WriteIssue = instructionIssue.valid && instructionIssue.bits.writeV0
+    val lsuWriteSet = maskAnd(
+      lsuWriteV0(laneIndex).valid,
+      indexToOH(lsuWriteV0(laneIndex).bits, parameter.chainingSize)
+    ).asUInt
+    val v0WriteIssue = instructionIssue.valid && instructionIssue.bits.writeV0 && instructionIssue.bits.toLane
     val clear: UInt = instructionFinish(laneIndex)
     val updateOH = maskAnd(v0WriteIssue, issueIndex1H).asUInt
-    updateBooleanToken(updateOH, clear)
+    updateBooleanToken(updateOH | lsuWriteSet, clear)
   }
 
   val useV0AsMaskToken: UInt = Seq