[rtl] fix pop count.

chipsalliance · Nov 15, 2024 · 76530e0 · 76530e0
1 parent ec1f32e
commit 76530e0
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1/src/mask/MaskReduce.scala b/t1/src/mask/MaskReduce.scala
@@ -75,7 +75,7 @@ class MaskReduce(parameter: T1Parameter) extends Module {
   val widen:      Bool = reqReg.uop === "b001".U || reqReg.uop(2, 1) === "b11".U
   // eew1HReg(0) || (eew1HReg(1) && !widen)
   val needFold:   Bool = false.B
-  val writeEEW:   UInt = reqReg.eew + widen
+  val writeEEW:   UInt = Mux(pop, 2.U, reqReg.eew + widen)
   val writeEEW1H: UInt = UIntToOH(writeEEW)(2, 0)
   val writeMask:  UInt = Fill(2, writeEEW1H(2)) ## !writeEEW1H(0) ## true.B