[rtl] fix gather.

chipsalliance · Nov 12, 2024 · 8913475 · 8913475
1 parent eecf196
commit 8913475
Showing 1 changed file with 5 additions and 1 deletion.
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -633,6 +633,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   }
 
   // select execute group
+  val pipeReadFire: Vec[Bool] = Wire(Vec(parameter.laneNumber, Bool()))
   val selectExecuteReq: Seq[ValidIO[MaskUnitReadReq]] = exeReqReg.zipWithIndex.map { case (_, index) =>
     val res: ValidIO[MaskUnitReadReq] = WireInit(0.U.asTypeOf(Valid(new MaskUnitReadReq(parameter))))
     res.bits.vs           := instReg.vs2 + readIssueStageState.vsGrowth(index)
@@ -649,6 +650,9 @@ class MaskUnit(parameter: T1Parameter) extends Module {
         res.valid := true.B
         res.bits  := readVS1Req
       }
+      pipeReadFire(index) := res.valid && !readVs1Valid && readCrossBar.input(index).ready
+    } else {
+      pipeReadFire(index) := res.valid && readCrossBar.input(index).ready
     }
     res
   }
@@ -666,7 +670,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   }
 
   // read control register update
-  val readFire:           UInt = VecInit(readCrossBar.input.map(_.fire)).asUInt
+  val readFire:           UInt = pipeReadFire.asUInt
   val anyReadFire:        Bool = readFire.orR
   val readStateUpdate:    UInt = readFire | readIssueStageState.groupReadState
   val groupReadFinish:    Bool = readStateUpdate === readIssueStageState.needRead