[rtl] fix masked write.

chipsalliance · Nov 12, 2024 · eecf196 · eecf196
1 parent c2f2846
commit eecf196
Showing 1 changed file with 5 additions and 3 deletions.
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -210,7 +210,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   // viota mask read vs2. Also pretending to be reading vs1
   val viotaReq:    Bool            = instReq.bits.decodeResult(Decoder.topUop) === "b01000".U
   when(instReq.valid && viotaReq || gatherRequestFire) {
-    instReg.vs1 := instReq.bits.vs2
+    instReg.vs1              := instReq.bits.vs2
     instReg.instructionIndex := instReq.bits.instructionIndex
   }
   // register for read vs1
@@ -1008,11 +1008,13 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   maskedWrite.needWAR := maskDestinationType
   maskedWrite.vd      := instReg.vd
   maskedWrite.in.zipWithIndex.foreach { case (req, index) =>
-    req.valid             := executeValid
+    val bitMask    = cutUInt(currentMaskGroupForDestination, parameter.datapathWidth)(index)
+    val maskFilter = !maskDestinationType || bitMask.orR
+    req.valid             := executeValid && maskFilter
     req.bits.mask         := cutUIntBySize(executeWriteByteMask, parameter.laneNumber)(index)
     req.bits.data         := cutUInt(executeResult, parameter.datapathWidth)(index)
     req.bits.pipeData     := exeReqReg(index).bits.source1
-    req.bits.bitMask      := cutUInt(currentMaskGroupForDestination, parameter.datapathWidth)(index)
+    req.bits.bitMask      := bitMask
     req.bits.groupCounter := executeDeqGroupCounter
     req.bits.ffoByOther   := compressUnit.out.ffoOutput(index) && ffo
     if (index == 0) {