[rtl] Mask type instructions need to wait until the mask unit ends.

chipsalliance · May 31, 2024 · 769f1ed · 769f1ed
1 parent 1fa3ace
commit 769f1ed
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Showing 3 changed files with 8 additions and 3 deletions.
diff --git a/t1/src/Bundles.scala b/t1/src/Bundles.scala
@@ -473,6 +473,7 @@ class VRFInstructionState extends Bundle {
   // execute finish, wait for write queue clear
   val wWriteQueueClear: Bool = Bool()
   val wLaneLastReport: Bool = Bool()
+  val wTopLastReport: Bool = Bool()
   val wLaneClear: Bool = Bool()
 }
 

diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -1117,6 +1117,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   // load need wait for write queue clear in lsu write queue
   vrf.instructionWriteReport.bits.state.wWriteQueueClear := !(laneRequest.bits.loadStore && !laneRequest.bits.store)
   vrf.instructionWriteReport.bits.state.wLaneLastReport := !laneRequest.valid
+  vrf.instructionWriteReport.bits.state.wTopLastReport := !laneRequest.bits.decodeResult(Decoder.maskUnit)
   vrf.instructionWriteReport.bits.state.wLaneClear := false.B
 
   val elementSizeForOneRegister: Int = parameter.vLen / parameter.datapathWidth / parameter.laneNumber

diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala
@@ -467,13 +467,16 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
       val elementUpdate1H: UInt = (writeUpdate1HVec ++ loadUpdate1HVec).reduce(_ | _)
       val dataInLaneCheck = ohCheck(dataInLane, record.bits.instIndex, parameter.chainingSize)
       val laneLastReport = ohCheck(instructionLastReport, record.bits.instIndex, parameter.chainingSize)
-      val lsuFinish = ohCheck(lsuLastReport, record.bits.instIndex, parameter.chainingSize)
+      val topLastReport = ohCheck(lsuLastReport, record.bits.instIndex, parameter.chainingSize)
       // only wait lane clear
-      val waitLaneClear = record.bits.state.stFinish && record.bits.state.wWriteQueueClear && record.bits.state.wLaneLastReport
+      val waitLaneClear =
+        record.bits.state.stFinish && record.bits.state.wWriteQueueClear &&
+          record.bits.state.wLaneLastReport && record.bits.state.wTopLastReport
       val stateClear: Bool = waitLaneClear && record.bits.state.wLaneClear
 
-      when(lsuFinish) {
+      when(topLastReport) {
         record.bits.state.stFinish := true.B
+        record.bits.state.wTopLastReport := true.B
       }
 
       when(laneLastReport) {