[rtl] delete token for feedback.

chipsalliance · May 31, 2024 · 1fa3ace · 1fa3ace
1 parent bcf6dec
commit 1fa3ace
Showing 1 changed file with 4 additions and 20 deletions.
diff --git a/t1/src/laneStage/SlotTokenManager.scala b/t1/src/laneStage/SlotTokenManager.scala
@@ -76,6 +76,8 @@ class SlotTokenManager(parameter: LaneParameter) extends Module {
   @public
   val responseReport: ValidIO[UInt] = IO(Flipped(Valid(UInt(parameter.instructionIndexBits.W))))
 
+  // Feedback is not accurate (index load may have already finished the instruction)
+  // In fact, we don’t really need to observe feedback
   @public
   val responseFeedbackReport: ValidIO[UInt] = IO(Flipped(Valid(UInt(parameter.instructionIndexBits.W))))
 
@@ -114,19 +116,6 @@ class SlotTokenManager(parameter: LaneParameter) extends Module {
     VecInit(tokenData.map(_ =/= 0.U)).asUInt
   }
 
-  // todo: Precise feedback
-  def feedbackUpdate(tokenData: Seq[UInt], enqWire: UInt, deqWire: UInt): UInt = {
-    tokenData.zipWithIndex.foreach { case (t, i) =>
-      val e = enqWire(i)
-      val d = deqWire(i)
-      val change = Mux(e, 1.U(tokenWith.W), -1.S(tokenWith.W).asUInt)
-      when((e ^ d) && (e || t =/= 0.U)) {
-        t := t + change
-      }
-    }
-    VecInit(tokenData.map(_ =/= 0.U)).asUInt
-  }
-
   val instructionInSlot: UInt = enqReports.zipWithIndex.map { case (enqReport, slotIndex) =>
 
     val writeToken: Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
@@ -145,7 +134,7 @@ class SlotTokenManager(parameter: LaneParameter) extends Module {
 
     if (slotIndex == 0) {
       val responseToken: Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
-      val feedbackToken: Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
+      // val feedbackToken: Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
       val crossWriteTokenLSB: Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
       val crossWriteTokenMSB: Seq[UInt] = Seq.tabulate(parameter.chainingSize)(_ => RegInit(0.U(tokenWith.W)))
 
@@ -169,13 +158,8 @@ class SlotTokenManager(parameter: LaneParameter) extends Module {
       val responseDoDeq: UInt =
         maskAnd(responseReport.valid, indexToOH(responseReport.bits, parameter.chainingSize)).asUInt
 
-      val feedbackDoDeq: UInt =
-        maskAnd(responseFeedbackReport.valid, indexToOH(responseFeedbackReport.bits, parameter.chainingSize)).asUInt
-
       val pendingResponse = tokenUpdate(responseToken, responseDoEnq, responseDoDeq)
-      // todo: Precise feedback
-      val pendingFeedback = feedbackUpdate(feedbackToken, responseDoEnq, feedbackDoDeq)
-      pendingSlotWrite | pendingCrossWriteLSB | pendingCrossWriteMSB | pendingResponse | pendingFeedback
+      pendingSlotWrite | pendingCrossWriteLSB | pendingCrossWriteMSB | pendingResponse
     } else {
       pendingSlotWrite
     }