[rtl] fix read queue.

chipsalliance · Nov 15, 2024 · ec1f32e · ec1f32e
1 parent b3a8c04
commit ec1f32e
Showing 1 changed file with 5 additions and 1 deletion.
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -775,7 +775,11 @@ class MaskUnit(parameter: T1Parameter) extends Module {
     }
 
     // pipe read fire
-    val pipeRead   = Pipe(readChannel(index).fire, sourceLane, readVRFLatency)
+    val pipeRead   = Pipe(
+      readChannel(index).fire && !maskDestinationType,
+      sourceLane,
+      readVRFLatency
+    )
     val pipeOffset = Pipe(readChannel(index).fire, request.bits.dataOffset, readVRFLatency)
     write1HPipe(index)    := Mux(pipeRead.valid, pipeRead.bits, 0.U(parameter.laneNumber.W))
     pipeDataOffset(index) := pipeOffset.bits