[doc] refactor and add all attributes

chipsalliance · Jun 21, 2024 · 32c7a5c · 32c7a5c
1 parent e51570b
commit 32c7a5c
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Showing 80 changed files with 6,208 additions and 1,062 deletions.
diff --git a/t1/src/Bundles.scala b/t1/src/Bundles.scala
@@ -135,7 +135,7 @@ class ExtendInstructionType extends Bundle {
 class LaneRequest(param: LaneParameter) extends Bundle {
   val instructionIndex: UInt = UInt(param.instructionIndexBits.W)
   // decode
-  val decodeResult: DecodeBundle = Decoder.bundle(param.fpuEnable)
+  val decodeResult: DecodeBundle = Decoder.bundle(param.decoderParam)
   val loadStore:    Bool = Bool()
   val issueInst:    Bool = Bool()
   val store:        Bool = Bool()
@@ -506,7 +506,7 @@ class InstructionPipeBundle(parameter: T1Parameter) extends Bundle {
   // 原始指令信息
   val request: VRequest = new VRequest(parameter.xLen)
   // decode 的结果
-  val decodeResult: DecodeBundle = new DecodeBundle(Decoder.all(parameter.fpuEnable))
+  val decodeResult: DecodeBundle = new DecodeBundle(Decoder.allFields(parameter.decoderParam))
   // 这条指令被vector分配的index
   val instructionIndex: UInt = UInt(parameter.instructionIndexBits.W)
   // 指令的csr信息
@@ -632,7 +632,7 @@ class LaneExecuteStage(parameter: LaneParameter)(isLastSlot: Boolean) extends Bu
   val sSendResponse: Option[Bool] = Option.when(isLastSlot)(Bool())
 
   // pipe state for stage3
-  val decodeResult: DecodeBundle = Decoder.bundle(parameter.fpuEnable)
+  val decodeResult: DecodeBundle = Decoder.bundle(parameter.decoderParam)
   val instructionIndex: UInt = UInt(parameter.instructionIndexBits.W)
   val loadStore: Bool = Bool()
   val vd: UInt = UInt(5.W)
@@ -656,7 +656,7 @@ class ExecutionUnitRecord(parameter: LaneParameter)(isLastSlot: Boolean) extends
   val maskType: Bool = Bool()
   val laneIndex: UInt = UInt(parameter.laneNumberBits.W)
   // pipe state
-  val decodeResult: DecodeBundle = Decoder.bundle(parameter.fpuEnable)
+  val decodeResult: DecodeBundle = Decoder.bundle(parameter.decoderParam)
 }
 
 class SlotRequestToVFU(parameter: LaneParameter) extends Bundle {

diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -10,7 +10,7 @@ import chisel3.probe.{Probe, ProbeValue, define}
 import chisel3.properties.{AnyClassType, Class, ClassType, Path, Property}
 import chisel3.util._
 import chisel3.util.experimental.decode.DecodeBundle
-import org.chipsalliance.t1.rtl.decoder.Decoder
+import org.chipsalliance.t1.rtl.decoder.{Decoder, DecoderParam}
 import org.chipsalliance.t1.rtl.lane._
 import org.chipsalliance.t1.rtl.vrf.{RamType, VRF, VRFParam, VRFProbe}
 
@@ -80,6 +80,7 @@ case class LaneParameter(
                           fpuEnable:                        Boolean,
                           portFactor:                       Int,
                           vrfRamType:                       RamType,
+                          decoderParam:                     DecoderParam,
                           vfuInstantiateParameter: VFUInstantiateParameter)
     extends SerializableModuleParameter {
 
@@ -469,10 +470,10 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   val requestVec: Vec[SlotRequestToVFU] = Wire(Vec(parameter.chainingSize, new SlotRequestToVFU(parameter)))
 
   /** decode message for [[requestVec]]. */
-  val executeDecodeVec: Vec[DecodeBundle] = Wire(Vec(parameter.chainingSize, Decoder.bundle(parameter.fpuEnable)))
+  val executeDecodeVec: Vec[DecodeBundle] = Wire(Vec(parameter.chainingSize, Decoder.bundle(parameter.decoderParam)))
 
   /** decode message for [[responseVec]]. */
-  val responseDecodeVec: Vec[DecodeBundle] = Wire(Vec(parameter.chainingSize, Decoder.bundle(parameter.fpuEnable)))
+  val responseDecodeVec: Vec[DecodeBundle] = Wire(Vec(parameter.chainingSize, Decoder.bundle(parameter.decoderParam)))
 
   /** response from vfu to slot. */
   val responseVec: Vec[ValidIO[VFUResponseToSlot]] = Wire(Vec(parameter.chainingSize, Valid(new VFUResponseToSlot(parameter))))

diff --git a/t1/src/T1.scala b/t1/src/T1.scala
@@ -13,7 +13,7 @@ import chisel3.probe.{Probe, ProbeValue, define, force}
 import chisel3.properties.{AnyClassType, Class, ClassType, Property}
 import chisel3.util.experimental.BitSet
 import org.chipsalliance.rvdecoderdb.Instruction
-import org.chipsalliance.t1.rtl.decoder.{Decoder, T1CustomInstruction}
+import org.chipsalliance.t1.rtl.decoder.{Decoder, DecoderParam, T1CustomInstruction}
 import org.chipsalliance.t1.rtl.lsu.{LSU, LSUParameter, LSUProbe}
 import org.chipsalliance.t1.rtl.vrf.{RamType, VRFParam, VRFProbe}
 
@@ -113,8 +113,11 @@ case class T1Parameter(
          |""".stripMargin}}
        |""".stripMargin
 
-  // FIXME
-  def allInstuctions: Set[Instruction] = Set.empty
+  val allInstructions: Seq[Instruction] = {
+    org.chipsalliance.rvdecoderdb.instructions(org.chipsalliance.rvdecoderdb.extractResource(getClass.getClassLoader))
+      .filter(instruction => instruction.instructionSet.name == "rv_v")++
+      t1customInstructions.map(_.instruction)
+  }.toSeq.sortBy(_.instructionSet.name)
 
   require(extensions.forall(Seq("Zve32x", "Zve32f").contains), "unsupported extension.")
   // TODO: require bank not overlap
@@ -213,6 +216,8 @@ case class T1Parameter(
   // and the values are their respective delays.
   val crossLaneConnectCycles: Seq[Seq[Int]] = Seq.tabulate(laneNumber)(_ => Seq(1, 1))
 
+  val decoderParam: DecoderParam = DecoderParam(fpuEnable, allInstructions)
+
   /** parameter for TileLink. */
   val tlParam: TLBundleParameter = TLBundleParameter(
     a = TLChannelAParameter(physicalAddressWidth, sourceWidth, memoryDataWidthBytes * 8, sizeWidth, maskWidth),
@@ -233,6 +238,7 @@ case class T1Parameter(
       fpuEnable = fpuEnable,
       portFactor = vrfBankSize,
       vrfRamType = vrfRamType,
+      decoderParam = decoderParam,
       vfuInstantiateParameter = vfuInstantiateParameter
     )
   /** Parameter for each LSU. */
@@ -313,7 +319,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
   /** the LSU Module */
 
   val lsu: Instance[LSU] = Instantiate(new LSU(parameter.lsuParameters))
-  val decode: Instance[VectorDecoder] = Instantiate(new VectorDecoder(parameter.fpuEnable))
+  val decode: Instance[VectorDecoder] = Instantiate(new VectorDecoder(parameter.decoderParam))
 
   // TODO: cover overflow
   // TODO: uarch doc about the order of instructions

diff --git a/t1/src/VectorDecoder.scala b/t1/src/VectorDecoder.scala
@@ -6,14 +6,14 @@ package org.chipsalliance.t1.rtl
 import chisel3._
 import chisel3.experimental.hierarchy.{instantiable, public}
 import chisel3.util.experimental.decode._
-import org.chipsalliance.t1.rtl.decoder.Decoder
+import org.chipsalliance.t1.rtl.decoder.{Decoder, DecoderParam}
 
 @instantiable
-class VectorDecoder(fpuEnable: Boolean) extends Module {
+class VectorDecoder(param: DecoderParam) extends Module {
   @public
   val decodeInput: UInt = IO(Input(UInt(32.W)))
   @public
-  val decodeResult: DecodeBundle = IO(Output(new DecodeBundle(Decoder.all(fpuEnable))))
+  val decodeResult: DecodeBundle = IO(Output(new DecodeBundle(Decoder.allFields(param))))
 
-  decodeResult := Decoder.decode(fpuEnable)(decodeInput)
+  decodeResult := Decoder.decode(param)(decodeInput)
 }