[doc] prepare T1CustomInstruction

chipsalliance · Jun 21, 2024 · e51570b · e51570b
1 parent 8be78ef
commit e51570b
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Showing 6 changed files with 28 additions and 1 deletion.
diff --git a/configgen/generated/blastoise.json b/configgen/generated/blastoise.json
@@ -5,6 +5,7 @@
     "extensions": [
       "Zve32f"
     ],
+    "t1customInstructions": [],
     "lsuBankParameters": [
       {
         "name": "scalar",

diff --git a/configgen/generated/machamp.json b/configgen/generated/machamp.json
@@ -5,6 +5,7 @@
     "extensions": [
       "Zve32x"
     ],
+    "t1customInstructions": [],
     "lsuBankParameters": [
       {
         "name": "scalar",

diff --git a/configgen/generated/sandslash.json b/configgen/generated/sandslash.json
@@ -5,6 +5,7 @@
     "extensions": [
       "Zve32x"
     ],
+    "t1customInstructions": [],
     "lsuBankParameters": [
       {
         "name": "scalar",

diff --git a/configgen/src/Main.scala b/configgen/src/Main.scala
@@ -8,8 +8,10 @@ import chisel3.util.{BitPat, log2Ceil}
 import chisel3.util.experimental.BitSet
 import mainargs._
 import org.chipsalliance.t1.rtl._
+import org.chipsalliance.t1.rtl.decoder.T1CustomInstruction
 import org.chipsalliance.t1.rtl.lsu.LSUInstantiateParameter
 import org.chipsalliance.t1.rtl.vrf.RamType
+
 import java.util.LinkedHashMap
 
 object Main {
@@ -67,6 +69,7 @@ object Main {
       vLen,
       dLen,
       extensions = Seq("Zve32f"),
+      t1customInstructions = Nil,
       lsuBankParameters =
         // scalar bank 0-1G
         Seq(
@@ -138,6 +141,7 @@ object Main {
       vLen,
       dLen,
       extensions = Seq("Zve32x"),
+      t1customInstructions = Nil,
       // banks=8 dLen=512 beatbyte16
       lsuBankParameters =
         // scalar bank 0-1G
@@ -215,6 +219,7 @@ object Main {
       vLen,
       dLen,
       extensions = Seq("Zve32x"),
+      t1customInstructions = Nil,
       lsuBankParameters =
         // scalar bank 0-1G
         Seq(

diff --git a/t1/src/T1.scala b/t1/src/T1.scala
@@ -12,7 +12,8 @@ import tilelink.{TLBundle, TLBundleParameter, TLChannelAParameter, TLChannelDPar
 import chisel3.probe.{Probe, ProbeValue, define, force}
 import chisel3.properties.{AnyClassType, Class, ClassType, Property}
 import chisel3.util.experimental.BitSet
-import org.chipsalliance.t1.rtl.decoder.Decoder
+import org.chipsalliance.rvdecoderdb.Instruction
+import org.chipsalliance.t1.rtl.decoder.{Decoder, T1CustomInstruction}
 import org.chipsalliance.t1.rtl.lsu.{LSU, LSUParameter, LSUProbe}
 import org.chipsalliance.t1.rtl.vrf.{RamType, VRFParam, VRFProbe}
 
@@ -84,6 +85,7 @@ case class T1Parameter(
   vLen:                    Int,
   dLen:                    Int,
   extensions:              Seq[String],
+  t1customInstructions:    Seq[T1CustomInstruction],
   // LSU
   lsuBankParameters:       Seq[LSUBankParameter],
   // Lane
@@ -111,6 +113,9 @@ case class T1Parameter(
          |""".stripMargin}}
        |""".stripMargin
 
+  // FIXME
+  def allInstuctions: Set[Instruction] = Set.empty
+
   require(extensions.forall(Seq("Zve32x", "Zve32f").contains), "unsupported extension.")
   // TODO: require bank not overlap
   /** xLen of T1, we currently only support 32. */

diff --git a/t1/src/decoder/T1CustomInstruction.scala b/t1/src/decoder/T1CustomInstruction.scala
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2022 Jiuyang Liu <[email protected]>
+
+package org.chipsalliance.t1.rtl.decoder
+
+import org.chipsalliance.rvdecoderdb.Instruction
+
+object T1CustomInstruction {
+  implicit def rw: upickle.default.ReadWriter[T1CustomInstruction] = upickle.default.macroRW[T1CustomInstruction]
+}
+
+// TODO: other field will be fill in the future, e.g. something that user can config, e.g.
+//       readRS1, readRD?
+case class T1CustomInstruction(instruction: Instruction)