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Caliptra core 2.0 HW spec updates #621

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Oct 30, 2024
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Caliptra core 2.0 HW spec updates #621

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883bafe
Caliptra core 2.0 HW spec updates
bharatpillilli Oct 29, 2024
52070c6
Update CaliptraHardwareSpecification.md - includes Caleb's feedback
bharatpillilli Oct 29, 2024
2f06cde
Update CaliptraHardwareSpecification.md - picture update
bharatpillilli Oct 29, 2024
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Add files via upload
bharatpillilli Oct 29, 2024
d829b01
Update CaliptraHardwareSpecification.md - fixed PSEL
bharatpillilli Oct 29, 2024
6cd75c8
Update CaliptraHardwareSpecification.md - fixes
bharatpillilli Oct 29, 2024
3580dcf
Update CaliptraHardwareSpecification.md - more fixes
bharatpillilli Oct 29, 2024
cc65883
Update CaliptraHardwareSpecification.md - removed SPI, UART reference…
bharatpillilli Oct 30, 2024
c779ea2
Update CaliptraHardwareSpecification.md - KV change updates
bharatpillilli Oct 30, 2024
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Update CaliptraHardwareSpecification.md - fixed block wording to seed
bharatpillilli Oct 30, 2024
ce158df
Update CaliptraHardwareSpecification.md - Caleb's wants :-)
bharatpillilli Oct 30, 2024
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6 changes: 3 additions & 3 deletions docs/CaliptraHardwareSpecification.md
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Expand Up @@ -474,13 +474,13 @@ When the RV core wakes up, all clocks are enabled. However, when the core is hal

Activity on the AXI interface only wakes up the SoC IFC clock. All other clocks remain off until any other condition is met or the core exits the halt state.
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| Cpu_halt_status | PSEL | Generic input wires <br>\|\| fatal error <br>\|\| debug/scan mode <br> \|\|JTAG access | Expected behavior |
| Cpu_halt_status | axi_active | Generic input wires <br>\|\| fatal error <br>\|\| debug/scan mode <br> \|\|JTAG access | Expected behavior |
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| :-------------- | :--- | :---------- | :-------------- |
| 0 | X | X | All gated clocks active |
| 1 | 0 | 0 | All gated clocks inactive |
| 1 | 0 | 1 | All gated clocks active (as long as condition is true) |
| 1 | 1 | 0 | Soc_ifc_clk_cg active (as long as PSEL = 1) <br>All other clks inactive |
| 1 | 1 | 1 | Soc_ifc_clk_cg active (as long as condition is true OR PSEL = 1) <br>All other clks active (as long as condition is true) |
| 1 | 1 | 0 | Soc_ifc_clk_cg active (as long as axi_active = 1) <br>All other clks inactive |
| 1 | 1 | 1 | Soc_ifc_clk_cg active (as long as condition is true OR axi_active = 1) <br>All other clks active (as long as condition is true) |

### Usage

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