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Adam edited this page Feb 27, 2013 · 1 revision

Table of Contents

VLAN tag handler

Project summary

Status :
Released
Version :
1.0.1
Authors :
Tatsuya Yabe
NetFPGA base source :
2.1.1

Introduction

This design adds/modifies/removes VLAN tags to outgoing packets. Operations(add/mod/remove) and VLAN tag values can be configured per port via registers. The forwarding ports for each input port are also programmable.

Download

Install from NetFPGA Yum repository

  1. Install the NetFPGA Base Package

Obtain Project Tarball

Download from Here

Regression Tests

The regression tests verify the functionality of this project. In order to run the tests, you need to have the machine connected for the regression tests as stated in the Run Regression Tests section of the Guide.

After connecting the cables, type the following command to run the regression tests. 

 nf_regress_test.pl --project vlan_tag_handler

Regression Tests

Test 1: Simple loopback test

Name :
test_loopback_simple
Description :
This test checks the programmability of forwarding ports. In this test, packets are sent from a CPU port to the corresponding MAC port, which has been setup by writing a value to the register. Outgoing packets are loopbacked in external PHY chip and sent back to the same NetFPGA MAC port. And then the packets should be sent back to the same CPU port, which has also been setup via register. The test compares if the received packets are equal to the sent packets. It also checks if the packet count is correct. This test exercises all four physical ports. This test doesn't use external NIC.
Location
projects/vlan_tag_handler/regress/test_loopback_simple
Output 
 SUCCESS!

Test 2: Passthrough test with VLAN tagged packets

Name :
test_vlan_through
Description :
This test checks the 'pass through' functionality. In this test, packets are sent from an external NIC to the cabled NetFPGA port and then reaches to FPGA's MAC port. In the FPGA, the packets are forwarded to the different NetFPGA port, which has been configured via registers (in this test, nf2c0 and nf2c1 are connected each other). Then the packets are received on the other NIC port. Since this is 'pass through' mode, this design shouldn't do anything to the packets. The test compares if the received packets are equal to the sent packets. It also checks if the packet count is correct. This test exercises nf2c0 and nf2c1 ports. This test uses external NIC.
Location
projects/vlan_tag_handler/regress/test_vlan_through
Output 
 SUCCESS!

Test 3: Passthrough test with non-VLAN packets

Name :
test_wo_vlan_through
Description :
Same test as test_vlan_through, except that the sent and expected packets don't have VLAN tags in this test.
Location
projects/vlan_tag_handler/regress/test_wo_vlan_through
Output 
 SUCCESS!

Test 4: VLAN ID-add test

Name :
test_vlan_add
Description :
This test checks the 'VLAN tag addition' functionality. In this test, packets without VLAN tags are sent from an external NIC to NetFPGA port, just as same as the tests above. In the FPGA, the packets are forwarded to the different NetFPGA port, which has been configured via registers (same configuration as the other tests). Then NetFPGA adds VLAN tags to them and send them out. The packets should be received on the other NIC port. The test compares if the recieved packets have expected VLAN tags and the other portions are equal to the sent packets. It also checks if the packet count is correct. This test exercises nf2c0 and nf2c1 ports. This test uses external NIC.
Location
projects/vlan_tag_handler/regress/test_vlan_add
Output 
 SUCCESS!

Test 5: VLAN ID-modify test

Name :
test_vlan_mod
Description :
This test checks the 'VLAN tag modification' functionality. In this test, packets WITH VLAN tags are sent from an external NIC to NetFPGA port, just as same as the tests above. In the FPGA, the packets are forwarded to the different NetFPGA port, which has been configured via registers (same configuration as the other tests). Then NetFPGA overrides VLAN tags from the received one to the one specified in the register, and sends them out. The packets should be received on the other NIC port. The test compares if the received packets have VLAN tags which are modified and changed to the expected ones, and checks if the other portions are equal to the sent packets. It also checks if the packet count is correct. This test exercises nf2c0 and nf2c1 ports. This test uses external NIC.
Location
projects/vlan_tag_handler/regress/test_vlan_mod
Output 
 SUCCESS!

Test 6: VLAN ID-remove test

Name :
test_vlan_strip
Description :
This test checks the 'VLAN tag remove' functionality. In this test, packets with VLAN tags are sent from an external NIC to NetFPGA port, just as same as the tests above. In the FPGA, the packets are forwarded to the different NetFPGA port, which has been configured via registers (same configuration as the other tests). Then NetFPGA strips off the VLAN tags from the packets and sends them out. The packets should be received on the other NIC port. The test compares if the received packets don't have VLAN tags, and checks if the other portions are equal to the sent packets. It also checks if the packet count is correct. This test exercises nf2c0 and nf2c1 ports. This test uses external NIC.
Location
projects/vlan_tag_handler/regress/test_vlan_strip
Output 
 SUCCESS!

Usage

Preparation

Edit register-configuration file: 

 cd projects/vlan_tag_handler/sw/
 vi register_setup.sh

You will find 12 variables on the top part of the file. They are 8 registers for setup forwarding output-ports and 4 registers for VLAN tag description. See comments for each section and modify accordingly.

Cabling

Connect the cables as you described in the register setup file above.

Download bitfile

Download the project bitfile: 

 su 
 nf_download vlan_tag_handler.bit

Run the script

Run the script you have modified: 

 su
 cd projects/vlan_tag_handler/sw/
 ./register_setup.sh

Now you are ready to use this design.

Design description

Base design

reference_nic

Modules added or changed

vlan_remover (new)

This module is attached as the first module of user_data_path. It parses an incoming packet to see if it has VLAN ethernet type (0x8100). If it finds it, strip this field and throw it away, and strip next 16bits of VLAN tag field and insert it as a module header right after the IOQ module header. It also recalculates the packet size and replaces values in IOQ module header. So now the VLAN information resides in a module header and the packet itself doesn't have VLAN tags.

hardwire_lookup(existing module)

This module has 8 registers for specifying output ports per input port. It looks into IOQ header of each packet and see the source(input) port number. Then it rewrites DSTPORT section of the IOQ header according to register value corresponding to each incoming port number.

bram_output_queue(existing module)

This module is replaced from sram_rr_output_queue so that users can use SRAM for any additional functions.

vlan_adder(new)

This module is attached per port right after output_port_queue, meaning there are four of them in the design. Each of them has 1 register for specifying VLAN tagging action.

The module consists of two parts. In the first part, it checks the register, and if the register value is:

VLAN tag value (meaning add or modify):

  • It looks for a module header which has VLAN information. if it is found, replce VLAN tag to the value written in the register. If not, insert a module header with this VLAN information.
Pass through:
  • It doesn't do anything.
Remove:
  • It looks for a module header which has VLAN information. if it is found, it invalidates this info. If not, it doesn't do anything.
The latter part of the module puts back VLAN information from a module header to inside the packet with VLAN ethernet type attached. Then the module header for VLAN information is removed and the module recalculates the packet size again and rewrite the values in each IOQ header.
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