LogicalAnalyzer
-- Main.YoungCho - 01 Jun 2010
We introduce a Digital Logic Analyzer (aka. Debugger) for the NetFPGA platform. As the data flow (64bit wide data bus, 8 bit control bus and 1 bit Read -Write Signals ) going through different modules, there might be some errors which designers are willing to figure out. The NetFPGA Digital Logic Analyzer could capture the packets and store them in a verilog file that could be used for later simulations, even simulations without a NetFPGA board involved. It will be real data instead of dummy data designers usually feed in as a test bench file. In this way, designers have more flexibilities and ways to analyze their module and debug.
Install the NetFPGA Logic Analyzer
NetFPGA becomes widely applied in research and teaching of internet systems and networking systems. The number of new designs on NetFPGA board increases rapidly. The only available option of debugging a new module on NetFPGA board is to connect a JTAG interface with a PC and use software such as Xilinx ChipScope Pro to debug. Generally, Xilinx simulations use predefined data as input, for which users have to manually generate test bench files. More severely, any types of user input will lead to prediction and coarse system design. To eliminate these unbearable factors, the only method one could think of is to use real data.
However, the typical way of getting real data is extremely cumbersome since one has to make a PC connection, capture the data and convert it into a format which can be used for simulation. To automate all these processes, we designed a debug module which could be seamlessly inserted into user data path. We also implemented three types of packet-capture triggers: start capturing whenever there is data coming on the bus, capturing only when the valid bit is set and capturing after a particular pattern is encountered. More, our debug module will automatically convert data into a verilog file which can be used directly for later simulation.
