The NetFPGA platform enables users to build working prototypes of high-speed, hardware-accelerated networking systems. However, one roadblock is that a typical networking specialist with a software-side background will find the programming of the FPGA to be a challenge because of the need for hardware design and description skills. This paper introduces G, which is a high-level packet-centric language for describing packet processing specifications in an implementation-independent manner. This language can be compiled to give high-speed FPGA-based components. An extension has been produced that allows these components to be dropped easily into the data path of the standard NetFPGA framework. This allows a user to write and debug packet processing functions at a high-level in G, and then use these on the NetFPGA alongside other components designed in the traditional way.
Use of the Packet Xpress tool suite is intended for collaborators with Xilinx Labs. Use the contact information below to find out how to develop with PaX.
- Install Packet Xpress locally (includes G compiler)
- Configure environment variables
- $XILINX_PAX : root directory of G tool, e.g. install_dir/PacketXpress/
- $LIB_LOCATION : location of compiled Xilinx libraries (unisim, simprim, XilinxCoreLib)
- $MODELTECH : location of Modelsim installation location
- $PATH : should include $XILINX_PAX/bin and $MODELTECH/bin
- Download modified files
- NF2/bin/nf21_run_test.pl
- NF2/lib/Makefiles/synth_makefile.rules
- NF2/lib/Makefiles/synth_makefile.vars
- Download new files
- NF2/lib/g/Makefile
- NF2/lib/g/compile_sources.pl
- NF2/lib/g/create_wrapper.pl
- Download Infrastructure
- bridge_local_link_to_stanford.vhd
- bridge_stanford_to_local_link.vhd
- Source files: Modenv.tar.gz
- Write G description
- High level simulation
- Embed in NetFPGA system
- Create NetFPGA simulation data & simulate
- Implement and test
- Simple G test function
- G Source
[Http_check.txt]
- G Source
- Companion interface description
<interfaces>
<Packet name="packetin" technology="LocalLink" direction="input">
<data width="64" minimumLength = "544" maximumLength="1024"/>
<speed value = "1000" units = "Mbps"></speed>
</packet>
<Packet name="packetout" technology="LocalLink" direction="output">
<data width="64" minimumLength = "544" maximumLength="1024"></data>
<speed value = "1000" units = "Mbps"></speed>
</packet>
<Access name="VLAN_lookup" technology="sram" direction="output" readable="true" writable="false">
<data width="1"></data>
<address width="12"></address>
<speed value = "125" units = "MHz"></speed>
</access>
</interfaces>
- The gfv tool creates packet instances to exercise a G description
- Specify format values, the values packet fields should take
- pair value and size in bits
- enables exact values ... e.g. 0xAB
- enables ranges ... e.g. 0 .. 7
- enables choices ... e.g. [0x8100]
formatvalue test1 =( [0x8100 || 0x0800] : 16, 0x11112222 : 32, # : 16, 0..3 : 8 );
This formatvalue will produce 8 packet instances to exercise the system.
- Hierarchy is also supported
formatvalue test2 =( 0xcafefeedface : 48, 0x010203040506 : 48, : test1 // use values specified in test1 0x0800 : 16, # : 128 );
- Command to create packet instances (no hierarchy)
- gfv <myfile></myfile>.fv
- Command to create packet instances (with hierarchy)
- gfv -topFormatValue test2 <myfile></myfile>.fv
- The high level simulation tool is gsim
- input packet instances
- outputs resulting packets from running simulation
- command to run gsim
- gsim <myfile></myfile>.g
- combine gsim with gfv to specify input packet instances
- gfv -topFormatValue test2 <myfile></myfile>.fv || gsim <myfile></myfile>.g
- Create hardware
- run the compiler to transform the G description into hardware implementation
- ghwgen -o <outputdir></outputdir> <myfile></myfile>.g
- Create hardware wrapper to embed within NetFPGA enviornment
- creates toplevel Verilog module that instantiates
- G module
- protocol bridge to go from NetFPGA to G module's LocalLink
- protocol bridge to go from G module's LocalLink to NetFPGA
- create_wrapper.pl <myfile></myfile>.vhd
- creates toplevel Verilog module that instantiates
- Instantiate the wrapper in the data path
- Copy user_data_path.v from another reference project to your src/ directory
- e.g. NF2/lib/verilog/user_data_path/reference_user_data/src/
- Copy user_data_path.v from another reference project to your src/ directory
- Add wires/registers as necessary to successfully include G module
- Two possible placements in the reference router pipeline are shown below for one or more G modules
- Note: G modules support a single packet input and a single packet output.
- Create a test in the verif directory
- Test consists of
- config.txt - specifies finish time
- make_pkts.pl
- Snippet of creating a packet to simulate and then the expected result packet [Make_pkts.txt]
- Simulate using nf21_run_test.pl -- <testname></testname>
- this compiles all your source files and generates necessary cores
- Create regression tests in similar way to creating simulation tests
- modify regress.txt in NF2/projects to add your project to be tested
- create a test in regress directory
- tests consist of a run.pl to produce input packets and specify expected output packets
- modify tests.txt to include new regression test
- In synth directory, type 'make'
- executes hardware design flow
- results in a bitfile
- Load bitfile into NetFPGA hardware
- use command nf2_download <mybitfile></mybitfile>.bit
- Run regression tests
- use command nf21_regress_test.pl
- This runs all the regression tests that have been specified in regress.txt
- use command nf21_regress_test.pl
- Walk through instructions as used in CS 344
[pdf/Gproject.pdf] - Walk through presentation
Xlnx_ppt.tar.gz (Sorry, it wouldn't let me upload a ppt file)
- Walk through instructions as used in CS 344
These reference guides are included as part of the PaX installation.
- PaX Quick Start
- PaX User Guide
- G Introduction
- Language Reference Manual
- PaX Eclipse User Guide
- XLNXNetfpga.tar.gz