Backend end Pass

4. Backend-end Pass

A. Scheduling:

During scheduling, Light-HLS map the instructions to exact cycle in the runtime so they can be controlled by the FSM in FPGA implementation. The scheduling is processed at different levels, including functions, loops, basic blocks and individual instructions. Loop pipelining, dataflow and instruction chaining are considered during scheduling. Those partitioned arrays will be properly scheduled accesses to them without visible partitioning transformation in LLVM IR code. Moreover, sometimes, the partition selection requires remainder calculation which will lead to extra delay. Light-HLS will detect which MUX will need remainder calculation and consider that during scheduling.

B. Binding:

Each operation is realized on FPGA with certain resource. Light-HLS can help designers collect the information of each type of operation from VivadoHLS. Then, during resource binding, Light-HLS will map the operation to specific resource cost, according to the requirement of timing and the type and bitwidth of operands. In the binding, resource reuse, buffers for dataflow and operation chaining are considered.