Merge pull request #1321 from throwaway96/aeon-lwst-20240126

AEON: Add bt.lwst instruction
uxmal · Jan 26, 2024 · db92f93 · db92f93
2 parents 8ebe670 + 2237a0a
commit db92f93
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Showing 5 changed files with 22 additions and 1 deletion.
diff --git a/src/Arch/OpenRISC/Aeon/AeonDisassembler.cs b/src/Arch/OpenRISC/Aeon/AeonDisassembler.cs
@@ -504,9 +504,13 @@ private static Decoder<AeonDisassembler, Mnemonic, AeonInstruction> Create16bitI
                 Instr(Mnemonic.bt_trap, uimm1_4),                   // source
                 Instr(Mnemonic.bt_nop, uimm1_4));                   // source
 
+            var decoder100000_stack = Mask(0, 1, "  opc=100000",
+                Instr(Mnemonic.bt_swst____, MuStack(1, 4, 2, PrimitiveType.Word32), R5),
+                Instr(Mnemonic.bt_lwst____, Ru5, MuStack(1, 4, 2, PrimitiveType.Word32)));
+
             var decoder100000 = Select((5, 5), u => u == 0,
                 decoder100000_special,
-                Instr(Mnemonic.bt_swst____, MuStack(0, 5, 1, PrimitiveType.Word32), R5));    // guess
+                decoder100000_stack);
 
             var decoder100001_sub0 = Select((5, 5), u => u == 0,
                 Instr(Mnemonic.bt_rfe, InstrClass.Transfer | InstrClass.Return), // source

diff --git a/src/Arch/OpenRISC/Aeon/AeonRewriter.cs b/src/Arch/OpenRISC/Aeon/AeonRewriter.cs
@@ -143,6 +143,7 @@ public IEnumerator<RtlInstructionCluster> GetEnumerator()
                 case Mnemonic.bg_lhs__: RewriteLoadExt(PrimitiveType.Int16); break;
                 case Mnemonic.bn_lhz:
                 case Mnemonic.bg_lhz__: RewriteLoadExt(PrimitiveType.UInt16); break;
+                case Mnemonic.bt_lwst____:
                 case Mnemonic.bn_lwz:
                 case Mnemonic.bg_lwz: RewriteLoadExt(PrimitiveType.Word32); break;
                 case Mnemonic.bg_mfspr1__: RewriteMfspr(true); break;

diff --git a/src/Arch/OpenRISC/Aeon/Mnemonic.cs b/src/Arch/OpenRISC/Aeon/Mnemonic.cs
@@ -94,6 +94,7 @@ public enum Mnemonic
         bg_lhs__,
         bn_lhz,
         bg_lhz__,
+        bt_lwst____,
         bn_lwz,
         bg_lwz,
         bg_mfspr,

diff --git a/src/UnitTests/Arch/OpenRISC/AeonDisassemblerTests.cs b/src/UnitTests/Arch/OpenRISC/AeonDisassemblerTests.cs
@@ -460,6 +460,12 @@ public void AeonDis_bg_lhz__()
             AssertCode("bg.lhz?\tr3,0x3A46(r7)", "E8 67 3A 47");
         }
 
+        [Test]
+        public void AeonDis_bt_lwst____()
+        {
+            AssertCode("bt.lwst??\tr4,0x14(r1)", "80 8B");
+        }
+
         [Test]
         public void AeonDis_bn_lwz()
         {

diff --git a/src/UnitTests/Arch/OpenRISC/AeonRewriterTests.cs b/src/UnitTests/Arch/OpenRISC/AeonRewriterTests.cs
@@ -623,6 +623,15 @@ public void AeonRw_bg_lhz__()
                 "2|L--|r6 = CONVERT(v5, uint16, word32)");
         }
 
+        [Test]
+        public void AeonRw_bt_lwst____()
+        {
+            Given_HexString("815D");
+            AssertCode(     // bt.lwst??	r10,0x38(r1)
+                "0|L--|00100000(2): 1 instructions",
+                "1|L--|r10 = Mem0[r1 + 56<i32>:word32]");
+        }
+
         [Test]
         public void AeonRw_bn_lwz()
         {