v0.10.0

Add resync of frequency and phases, fix bug in sequence increment and added optional h-bridge DIO output on 7N, 7P

Major changes

Resync #90
H-Bridge #93

v0.8.2

Major changes

• Fix gain error introduced by CIC filter #86

Minor changes

• scpi-parser was updated to 2.2 #91
• Updated examples to use CairoMakie instead of PyPlot #92
• Allow multiple SCPI commands to be handled during data transmission/pipelining

v0.8.0

Major changes

• scpi-parser was updated to 2.3

Minor changes

• Setting and reading the DIOs in the wrong mode now issues a warning

v0.7.0

Bug fixes in triggering logic:

• Fix floating external trigger input for master RP
• Fix client timeout for large samplesPerStep during master trigger off

New calibration option allows limiting of maximum and minimum signal strength as [-1, ..., 1] of output strength

Add version tracking of FPGA image and warnings to client if non-matching versions are detected.

v0.6.0

Updated trigger options:

• Trigger distribution over SATA cable
• More varied cluster trigger setups
• Counter-based trigger option

Updated signal generation options:

• Added arbitrary waveform component to each channel
• Increased FPGA sequence buffer size and possible step size
• Increase number of sequence channel to 6: Two analog channel and four pins

Added additional filter to signal acquisition to compensate non-flat amplitude response of decimation filter

v0.5.0

Updated signal generation:

• Signal ramping
• Improved calibration behaviour
• Changed sequence to work with signal ramping
• Removed square waveform (will return in a later release)

Updated client-server communication:

• Allow for SCPI commands during sample transmission
• Client offers batch execution for faster configuration
• Improved communication performance (on Linux)
• Added return values to SCPI commands

v0.5.0-rc0

Release candidate for version 0.5.0

v0.4.2

Merge pull request #35 from tknopp/JS/Z7020

Add support for Zynq 7020-based Red Pitayas

v0.2.0

correct link