Introduce preliminary macro operation fusion

[qwe661234]

Through our observations, we have identified certain patterns in instruction sequences. By converting these specific RISC-V instruction patterns into faster and equivalent code, we can significantly improve execution efficiency.

In our current analysis, we focus on a commonly used benchmark and have found the following frequently occurring instruction patterns: auipc + addi, auipc + add, multiple sw, and multiple lw.

Metric	commit fba5802	macro fuse operation	Speedup
CoreMark	1351.065 (Iterations/Sec)	1352.843 (Iterations/Sec)	+0.13％
dhrystone	1073 DMIPS	1146 DMIPS	+6.8%
nqueens	8295 msec	7824 msec	+6.0%

[jserv]

To enhance execution efficiency, we employ instruction fusion by combining sequences that adhere to specific patterns into fused instructions. Currently, we have incorporated four fused instructions: auipc + addi, auipc + add, multiple sw, and multiple lw.

You shall show some numbers to illustrate how we can benefit from macro operation fusion.
In addition, why were 4 patterns were picked? Denote them with existing benchmark programs.

[jserv]

Is it possible to manipulate the sequence lui + addi?
See #81 (comment)

Disassembly of CoreMark:

   10324:       000087b7                lui     a5,0x8
   10328:       b0578793                addi    a5,a5,-1275 # 0x7b05

[qwe661234]

It is possible. however, there are some problems when running qrcode.elf if we import this pattern, so I skip it in this pull request.

[jserv]

It is possible. however, there are some problems when running qrcode.elf if we import this pattern, so I skip it in this pull request.

Add a comment starting with "FIXME: lui + addi"

[jserv]

lw is the most frequent instruction (see #34), and we might dive into its use case more.

[jserv]

Can you handle the following case? (disassembly from CoreMark

   10248:       03012603                lw      a2,48(sp)
   1024c:       01c11583                lh      a1,28(sp)
   10250:       03412503                lw      a0,52(sp)

[jserv]

In addition, consider the following scenario:

   10a84:       01c12083                lw      ra,28(sp)
   10a88:       07f47513                andi    a0,s0,127
   10a8c:       01812403                lw      s0,24(sp)
   10a90:       01412483                lw      s1,20(sp)
   10a94:       01012903                lw      s2,16(sp)
   10a98:       00c12983                lw      s3,12(sp)

It can be regarded as 5 lw. Roughly speaking, if peephole optimization can be applied, we shall benefit from further optimizations.

[jserv]

Another case: (disassembly from CoreMark)

   10c08:       01162023                sw      a7,0(a2)
   10c0c:       00052783                lw      a5,0(a0)
   10c10:       00059883                lh      a7,0(a1)
   10c14:       00259603                lh      a2,2(a1)
   10c18:       00f82023                sw      a5,0(a6)
   10c1c:       01052023                sw      a6,0(a0)
   10c20:       00e82223                sw      a4,4(a6)
   10c24:       0006a783                lw      a5,0(a3)

Mixture of sw and lw.

[qwe661234]

Another case: (disassembly from CoreMark)

   10c08:       01162023                sw      a7,0(a2)
   10c0c:       00052783                lw      a5,0(a0)
   10c10:       00059883                lh      a7,0(a1)
   10c14:       00259603                lh      a2,2(a1)
   10c18:       00f82023                sw      a5,0(a6)
   10c1c:       01052023                sw      a6,0(a0)
   10c20:       00e82223                sw      a4,4(a6)
   10c24:       0006a783                lw      a5,0(a3)

Mixture of sw and lw.

In this case, the memory address is not contiguous, what we can do just pack these instructions, but we cannot save any operation, such as checking misaligned.

[qwe661234]

In addition, consider the following scenario:

   10a84:       01c12083                lw      ra,28(sp)
   10a88:       07f47513                andi    a0,s0,127
   10a8c:       01812403                lw      s0,24(sp)
   10a90:       01412483                lw      s1,20(sp)
   10a94:       01012903                lw      s2,16(sp)
   10a98:       00c12983                lw      s3,12(sp)

It can be regarded as 5 lw. Roughly speaking, if peephole optimization can be applied, we shall benefit from further optimizations.

In this case, we can pack the last four instruction lw. if we want to handle this case by packing 5 lw, we need to reorder the instruction. For example, swap the first and the second instruction.

[qwe661234]

Can you handle the following case? (disassembly from CoreMark

   10248:       03012603                lw      a2,48(sp)
   1024c:       01c11583                lh      a1,28(sp)
   10250:       03412503                lw      a0,52(sp)

Ditto, if we want to handle this case, we need some strategies to reorder the instructions.

[jserv]

In this pull request, let's concentrate on preliminary support of macro operation fusion. You shall add some comments for further efforts such as instruction reordering.

[jserv]

Add some FIXME/TODO comments which address more macro operation fusion we can pay attention to.

[qwe661234]

Check CI failure.

In debug mode, the rv_step only emulates one instruction per step, specifically, it executes only the first instruction in a basic block then translate next basic block in PC + 4. If we apply macro fusion operations in debug mode, errors can occur. For instance, fusing auipc and addi and executing them together. However, the subsequent instruction is not a nop because the emulator only emulates the first instruction in a basic block. Consequently, the following instruction remains addi, resulting in an error because the result become auipc + addi + addi.

Therefore, we cannot do fuse operation in debug mode.