testsuite/synth: add more sources for verilog generate

testsuite/synth/generate01/gen1.v

@@ -0,0 +1,14 @@
+module oa8(input [7:0] a,
+	   input [7:0]	b,
+	   input [7:0]	c,
+	   output [7:0]	o);
+
+   genvar i;
+
+   generate
+      for (i = 0; i < 8; i=i+1) begin
+	 wire t = a[i] | b[i];
+	 assign o[i] = t & c[i];
+      end
+   endgenerate
+endmodule

testsuite/synth/generate01/gen2.v

@@ -0,0 +1,12 @@
+module oa8(input [7:0] a,
+	   input [7:0]	b,
+	   input [7:0]	c,
+	   output [7:0]	o);
+
+   genvar i;
+
+   for (i = 0; i < 8; i=i+1) begin
+      wire t = a[i] | b[i];
+      assign o[i] = t & c[i];
+   end
+endmodule

testsuite/synth/generate01/gen3.v

@@ -0,0 +1,12 @@
+module oa8(input [7:0] a,
+	   input [7:0]	b,
+	   input [7:0]	c,
+	   output [7:0]	o);
+
+   genvar i;
+
+   for (i = 0; i < 8; i=i+1) begin
+      or a_or_b(t, a[i], b[i]);
+      assign o[i] = t & c[i];
+   end
+endmodule

testsuite/synth/generate01/gen4.v

@@ -0,0 +1,19 @@
+module oa1(input a,
+	   input b,
+	   input c,
+	   output o);
+
+   assign o = (a | b) & c;
+endmodule
+
+module oa8(input [7:0] a,
+	   input [7:0]	b,
+	   input [7:0]	c,
+	   output [7:0]	o);
+
+   genvar i;
+
+   for (i = 0; i < 8; i=i+1) begin
+      oa1 gate(a[i], b[i], c[i], o[i]);
+   end
+endmodule