verilog-vhdl_export: discard more useless items

stefanlippuner · Feb 14, 2024 · ac67b4c · ac67b4c
1 parent 4f677dd
commit ac67b4c
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/src/verilog/verilog-vhdl_export.adb b/src/verilog/verilog-vhdl_export.adb
@@ -136,12 +136,14 @@ package body Verilog.Vhdl_Export is
                --   the identifier of the port.
                null;
             when N_Localparam
-              | N_Var =>
+              | N_Var
+              | N_Genvar =>
                null;
             when Nkinds_Nets
               | N_Assign
               | N_Module_Instance
               | N_Generate_Region
+              | N_Loop_Generate
               | N_Always
               | N_Initial =>
                null;