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Add RISC-V for XuanTie C908#115

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thisisjube wants to merge 55 commits intoslothy-optimizer:mainslothy-optimizer/slothy:mainfrom thisisjube:riscvthisisjube/slothy:riscvCopy head branch name to clipboard

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Commits

Commits on Oct 16, 2024

• feat: add risc-v example

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Commits on Oct 22, 2024

• refactor: adjust .gitignore

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• doc: start overview of RISC-V and C908

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Commits on Oct 23, 2024

• doc+feat: add notes for RISCV ISA and start adopting riscv model

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Commits on Oct 25, 2024

• feat: minimal riscv example works

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• feat: add Integer Register-Immediate Instructions

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Commits on Oct 26, 2024

• feat: add integer register-register ops

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Commits on Nov 6, 2024

• fix: make immediate parsing work, further research

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Commits on Nov 10, 2024

• feat: add load/ store instructions

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• fix: add forgotten instructions, fix typos

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• feat: implement <w>-specifier to indicate a dedicated 32-bit version for some instructions

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• refactor: restructure files and classes

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Commits on Nov 13, 2024

• fix: add all_subclasses_leaves() to correct class

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• refactor: change all_subclass_leaves from attribute to method

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• fix: move iter_riscv_instructions() to correct place

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• refactor: rename some files

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Commits on Nov 15, 2024

• feat: Introduce a factory method to dynamically create instruction classes from a list

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Commits on Nov 18, 2024

• feat: add m extension set

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• feat: add <w> for m extension set

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• feat: add new testing code, add register aliases

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Commits on Nov 19, 2024

• feat: add naive rv64im Dilithium NTTs from PQRV paper

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Commits on Nov 24, 2024

• feat: add uArch model

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• feat: optimize ntt_8l_singlissue_plant_rv64im.s

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• feat: further optimizations

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• feat: opt

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Commits on Dec 4, 2024

• feat: split ntt_dilithium example

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• fix: fix wrong instruction defs and register names

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• feat: first heuristic split optimization

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• refactor: update copyright headers

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• refactor: clean up code, reformat according to PEP-8 style

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• refactor: move instruction factory to RISCVInstruction class

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Commits on Dec 6, 2024

• doc: update todo

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• Merge branch 'main' into riscv

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• refactor: cleanup

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Commits on Dec 11, 2024

• fix: missing function renaming after optimization

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• feat: add timeout for risc-v example

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• fix: fix typos in XuanTie and rename optimized function for risc-v ntt_dilithium

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• fix: add missing constants in asm code

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• wip: add vector registers

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Commits on Dec 12, 2024

• feat: Add loop parsing to riscv model

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Commits on Dec 18, 2024

• feat: use loop optimization for dilithium

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• fix: typo in examples

  

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Commits on Jan 8, 2025

• fix: loop recogntion regex

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• fix: repair loop recognition

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• feat: add new optimized file

  

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• fix: final (tm) fix for loop recognition

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• feat: new opt

  

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• wip: try other values for latency and cpi

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• feat: new opt

  

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  5b5212b

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• feat: new opt

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• feat: new opt

  

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Commits on Jan 10, 2025

• wip: update uArch model

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  1333acd

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• wip: new opt

  

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• feat: add a testing file to examine the uArch

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Commits on Jan 15, 2025

• refactor: refactor poly_basemul test

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