Add RISC-V for XuanTie C908 #115
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…for some instructions The <w>-specifier allows having 32-bit and 64-bit versions of instructions in one class which saves some work. While parsing, mnemonics are compared first to find the matching class for an instruction. Since add<w> would not be identified as an add-instruction, we first must replace <w> (if present) by the corresponding regex pattern and call re.match(srcline, pattern) afterward. A generic solution for parsing specifiers which modify the mnemonic could be a future task.
The method is set as an attribute during each call of parser() atm. This assignment should happen at a proper place.
…asses from a list
* Limitation: Only supports loops that end in an addi and bge/bne
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Some initial review:
The new mechanism of how instructions can be added saves a lot of time and your new structure makes this complicated process more accesible. That's great!
Overall, the code looks well written. There are a few left overs from aarch64 that should be removed and we should discuss how to go about the hints. See the comments for a bit more details (and some nit picky details).
| @@ -1493,6 +1499,80 @@ def core(self, slothy): | |||
| slothy.config.sw_pipelining.optimize_postamble = False | |||
| slothy.optimize_loop("flt_radix4_fft_loop_start") | |||
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| class RISC_VExample0(Example): | |||
| def __init__(self, var="", arch=RISC_V, target=Target_XuanTieC908): | |||
| name = "riscv_simple0" | |||
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Suggestion: Have an actual "simple" and minimalistic example here instead of the full NTT code as this is also part of a separate example.
| slothy.config.variable_size=True | ||
| slothy.config.constraints.stalls_first_attempt=32 | ||
| slothy.config.inputs_are_outputs = True | ||
| slothy.config.outputs = ['x1', 'x2', 'x3', 'x4', 'x5', 'x6', 'x7', 'x8', 'x9', 'x10', |
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I think for the current example as it is, there are too many outputs defined here. For example x10, which corresponds to a0 is used as an input in the input assembly and thus automatically gets marked as an input due to slothy.config.inputs_are_outputs = True.
Generally, we should try to keep this list as small as it needs to be.
| // gap // .................... | ||
| str q3, [x0, #-16] // ...................* | ||
| // gap // .................... | ||
| // Instructions: 20 |
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I think changes to this file should not be part of this PR?
| """This module defines a bunch of custom slothy exceptions.""" | ||
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| class FatalParsingException(Exception): # done |
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What does "done" mean here?
| self.args_out_restrictions.append(None) | ||
| self.args_out.append(hint_register_name(tag)) | ||
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| # self.arg_types_out.append(RegisterType.HINT) |
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We should revisit how hints are used here.
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| return src | ||
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| flaglist = ["eq", "ne", "cs", "hs", "cc", "lo", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le"] |
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Do all these options exist in RISC-V? Is it exactly the same as aarch64?
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| @staticmethod | ||
| def get_parser(pattern): | ||
| """Build parser for given AArch64 instruction pattern""" |
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| from slothy.targets.riscv.instruction_core import Instruction | |||
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If this is deprecated, it can go?
| def add_further_constraints(slothy): | ||
| if slothy.config.constraints.functional_only: | ||
| return | ||
| add_slot_constraints(slothy) |
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Probably these should be removed here.
I think the constraints are not added anyways because we're not working with vectors yet, so no harm is caused, but it's just wrong.
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| def add_st_hazard(slothy): | ||
| def is_vec_st_st_pair(inst_a, inst_b): |
Adds an implementation for the RISC-V architecture on the XuanTie C908, initially supporting the RV32/64I and RV32/64M ISA extensions, with plans to include RV32/64V in the future. This PR also introduces a new structure for organizing files, classes, and related components. Additionally, it includes a mechanism to reduce the effort required to add new instructions by dynamically generating instruction classes from a simple list. Overall, the changes also aim to streamline the process of adding new architectures, making it faster and more straightforward.