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Remove insn_len field in IR structure
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qwe661234 committed Oct 11, 2023
1 parent 1dc4f9e commit 8cf53b3
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Showing 3 changed files with 10 additions and 14 deletions.
4 changes: 1 addition & 3 deletions src/decode.c
Original file line number Diff line number Diff line change
Expand Up @@ -1726,10 +1726,9 @@ bool rv_decode(rv_insn_t *ir, uint32_t insn)
/* If the last 2-bit is one of 0b00, 0b01, and 0b10, it is
* a 16-bit instruction.
*/
if ((insn & FC_OPCODE) != 3) {
if (is_compressed(insn)) {
insn &= 0x0000FFFF;
const uint16_t c_index = (insn & FC_FUNC3) >> 11 | (insn & FC_OPCODE);
ir->insn_len = INSN_16;

/* decode instruction (compressed instructions) */
const decode_t op = rvc_jump_table[c_index];
Expand All @@ -1740,7 +1739,6 @@ bool rv_decode(rv_insn_t *ir, uint32_t insn)

/* standard uncompressed instruction */
const uint32_t index = (insn & INSN_6_2) >> 2;
ir->insn_len = INSN_32;

/* decode instruction */
const decode_t op = rv_jump_table[index];
Expand Down
14 changes: 6 additions & 8 deletions src/decode.h
Original file line number Diff line number Diff line change
Expand Up @@ -246,11 +246,6 @@ enum {
};
/* clang-format on */

enum {
INSN_16 = 2,
INSN_32 = 4,
};

typedef struct {
int32_t imm;
uint8_t rd, rs1, rs2;
Expand All @@ -275,9 +270,6 @@ typedef struct rv_insn {

uint32_t pc;

/* instruction length */
uint8_t insn_len;

/* Tail-call optimization (TCO) allows a C function to replace a function
* call to another function or itself, followed by a simple return of the
* function's result, with a direct jump to the target function. This
Expand Down Expand Up @@ -308,3 +300,9 @@ typedef struct rv_insn {

/* decode the RISC-V instruction */
bool rv_decode(rv_insn_t *ir, const uint32_t insn);

/* Detect the instruction is RV32C or not */
FORCE_INLINE bool is_compressed(uint32_t insn)
{
return (insn & FC_OPCODE) != 3;
}
6 changes: 3 additions & 3 deletions src/emulate.c
Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@ enum {

static void rv_exception_default_handler(riscv_t *rv)
{
rv->csr_mepc += rv->compressed ? INSN_16 : INSN_32;
rv->csr_mepc += rv->compressed ? 2 : 4;
rv->PC = rv->csr_mepc; /* mret */
}

Expand Down Expand Up @@ -628,14 +628,14 @@ static void block_translate(riscv_t *rv, block_map_t *map, block_t *block)

/* decode the instruction */
if (!rv_decode(ir, insn)) {
rv->compressed = (ir->insn_len == INSN_16);
rv->compressed = is_compressed(insn);
rv_except_illegal_insn(rv, insn);
break;
}
ir->impl = dispatch_table[ir->opcode];
ir->pc = block->pc_end;
/* compute the end of pc */
block->pc_end += ir->insn_len;
block->pc_end += is_compressed(insn) ? 2 : 4;
block->n_insn++;
prev_ir = ir;
/* stop on branch */
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