reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (45)
hw/carfield.sv|2511 col 47| Binary literal 4'b1 has less digits than expected for 4 bits. [Style: number-literals] [undersized-binary-literal]
hw/carfield.sv|2517 col 101| Line length exceeds max: 100; is: 118 [Style: line-length] [line-length]
hw/carfield.sv|2518 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/carfield.sv|2519 col 101| Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
hw/carfield.sv|2520 col 101| Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
hw/carfield.sv|2521 col 101| Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
hw/carfield.sv|2522 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2523 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2527 col 101| Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]
hw/carfield.sv|2530 col 101| Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
hw/carfield.sv|2532 col 101| Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]
hw/carfield.sv|2534 col 101| Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]
hw/carfield.sv|2546 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2548 col 101| Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]
hw/carfield.sv|2552 col 101| Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
hw/carfield.sv|2554 col 101| Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
hw/carfield.sv|2556 col 101| Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
hw/carfield.sv|2558 col 101| Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
hw/carfield.sv|2560 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2562 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2563 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2564 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2565 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/carfield.sv|2566 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/carfield.sv|2567 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2568 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/carfield.sv|2569 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/carfield.sv|2571 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2573 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2574 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2575 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2576 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2577 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2578 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2589 col 101| Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]
hw/carfield.sv|2590 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2591 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2592 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2593 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2594 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2595 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2596 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2600 col 101| Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]
hw/carfield.sv|2601 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/carfield.sv|2602 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 2511 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2511
Binary literal 4'b1 has less digits than expected for 4 bits. [Style: number-literals] [undersized-binary-literal]
Raw output
message:"Binary literal 4'b1 has less digits than expected for 4 bits. [Style: number-literals] [undersized-binary-literal]" location:{path:"hw/carfield.sv" range:{start:{line:2511 column:47}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:2511 column:47} end:{line:2512}} text:" .APB_PSTROBE (4'b0001), // : in -- APB\n"}
Check warning on line 2517 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2517
Line length exceeds max: 100; is: 118 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 118 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2517 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2518 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2518
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2518 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2519 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2519
Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2519 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2520 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2520
Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2520 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2521 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2521
Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2521 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2522 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2522
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2522 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2523 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2523
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2523 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2527 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2527
Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2527 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2530 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2530
Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2530 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2532 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2532
Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2532 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2534 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2534
Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2534 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2546 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2546
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2546 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2548 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2548
Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2548 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2552 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2552
Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2552 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2554 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2554
Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2554 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2556 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2556
Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2556 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2558 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2558
Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2558 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2560 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2560
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2560 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2562 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2562
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2562 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2563 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2563
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2563 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2564 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2564
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2564 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2565 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2565
Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2565 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2566 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2566
Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2566 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 2567 in hw/carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/carfield.sv#L2567
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2567 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}