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First transparent streamer integration.
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Yvan Tortorella committed Apr 15, 2024
1 parent 3b43ae1 commit 5510f75
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2 changes: 1 addition & 1 deletion Bender.lock
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Expand Up @@ -499,7 +499,7 @@ packages:
- riscv-dbg
- tech_cells_generic
streamer:
revision: 83db53a8017c630f1c8bdc358d88b27067c01e56
revision: 41c90f7c525f45539afaa3387e3975c6e785a243
version: null
source:
Git: [email protected]:musa/streamer.git
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6 changes: 5 additions & 1 deletion Bender.yml
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Expand Up @@ -28,7 +28,7 @@ dependencies:
common_cells: { git: https://github.com/pulp-platform/common_cells.git, version: 1.31.1 }
pulp-ethernet: { git: https://github.com/pulp-platform/pulp-ethernet.git, rev: bdc8031ab270a49da28df269266ce9ab9a133636 } # branch: carfield
riscv-dbg: { git: https://github.com/pulp-platform/riscv-dbg.git, version: =0.8.0 }
streamer: { git: [email protected]:musa/streamer.git, rev: 83db53a8 } # branch: tech_lib_organization
streamer: { git: [email protected]:musa/streamer.git, rev: 41c90f7c } # branch: yt/integration

workspace:
package_links:
Expand All @@ -40,6 +40,10 @@ workspace:

sources:
# Configurations
- target: carfield_l2dual_secure_pulp_periph_can_streamer
files:
- hw/configs/carfield_l2dual_secure_pulp_periph_can_streamer.sv

- target: carfield_l2dual_safe_secure_pulp_spatz_periph_can
files:
- hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv
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2 changes: 1 addition & 1 deletion bender-common.mk
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Expand Up @@ -6,7 +6,7 @@
# Author: Matteo Perotti <[email protected]>

# Runtime-selectable Carfield configuration
CARFIELD_CONFIG ?= carfield_l2dual_secure_pulp_periph_can
CARFIELD_CONFIG ?= carfield_l2dual_secure_pulp_periph_can_streamer

# bender targets
common_targs += -t cva6
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2 changes: 1 addition & 1 deletion carfield.mk
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Expand Up @@ -20,7 +20,7 @@
CAR_ROOT ?= $(shell $(BENDER) path carfield)
CAR_HW_DIR := $(CAR_ROOT)/hw
CAR_SW_DIR := $(CAR_ROOT)/sw
CAR_TGT_DIR := $(CAR_ROOT)/target/
CAR_TGT_DIR := $(CAR_ROOT)/target
CAR_XIL_DIR := $(CAR_TGT_DIR)/xilinx
CAR_SIM_DIR := $(CAR_TGT_DIR)/sim
SECD_ROOT ?= $(shell $(BENDER) path opentitan)
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116 changes: 116 additions & 0 deletions hw/carfield.sv
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Expand Up @@ -2497,6 +2497,122 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care...
assign can_tx_o = '0;
assign apb_mst_rsp[CanIdx] = '0;
end

// Telemetry and Telecomand IP (Streamer)
if (carfield_configuration::StreamerEnable) begin: gen_streamer
localparam int unsigned StreamerAsyncIdx = CarfieldRegBusSlvIdx.streamer-NumSyncRegSlv;
TASI_top (
.SYS_CLK (periph_clk),
.ASYNC_RST_N (periph_rst_n), // FIXME: connect to dedicated one
.APB_PADD (apb_mst_req[StreamerIdx].paddr), // : in -- APB
.APB_PENABLE (apb_mst_req[StreamerIdx].penable), // : in -- APB
.APB_PPROT (3'b0), // : in -- APB
.APB_PSEL (apb_mst_req[StreamerIdx].psel), // : in -- APB
.APB_PSTROBE (4'b1), // : in -- APB

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/carfield.sv#L2511 

Binary literal 4'b1 has less digits than expected for 4 bits. [Style: number-literals] [undersized-binary-literal]
Raw output 
message:"Binary literal 4'b1 has less digits than expected for 4 bits. [Style: number-literals] [undersized-binary-literal]" location:{path:"hw/carfield.sv" range:{start:{line:2511 column:47}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:2511 column:47} end:{line:2512}} text:"      .APB_PSTROBE                        (4'b0001),                            // : in -- APB\n"}
.APB_PWDATA (apb_mst_req[StreamerIdx].pwdata), // : in -- APB
.APB_PWRITE (apb_mst_req[StreamerIdx].pwrite), // : in -- APB
.APB_PRDATA (apb_mst_rsp[StreamerIdx].prdata), // : out -- APB
.APB_PREADY (apb_mst_rsp[StreamerIdx].pready), // : out -- APB
.APB_PSLVERR (apb_mst_rsp[StreamerIdx].pslverr), // : out -- APB
.REG_ADDR (ext_reg_async_slv_data_out[StreamerAsyncIdx].addr[31:0]), // : in -- REG IF

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[verible-verilog-lint] hw/carfield.sv#L2517 

Line length exceeds max: 100; is: 118 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 118 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2517 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.REG_M_ID (3'b001), // : in std_logic_vector (2 downto 0); -- REG IF

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[verible-verilog-lint] hw/carfield.sv#L2518 

Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2518 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.REG_VALID (ext_reg_async_slv_data_out[StreamerAsyncIdx].valid), // : in -- REG IF

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[verible-verilog-lint] hw/carfield.sv#L2519 

Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2519 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.REG_WDATA (ext_reg_async_slv_data_out[StreamerAsyncIdx].wdata), // : in -- REG IF

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[verible-verilog-lint] hw/carfield.sv#L2520 

Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2520 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.REG_WRITE (ext_reg_async_slv_data_out[StreamerAsyncIdx].write), // : in -- REG IF

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[verible-verilog-lint] hw/carfield.sv#L2521 

Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2521 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.REG_RDATA (ext_reg_async_slv_data_in[StreamerAsyncIdx].rdata), // : out -- REG IF

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[verible-verilog-lint] hw/carfield.sv#L2522 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2522 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.REG_READY (ext_reg_async_slv_data_in[StreamerAsyncIdx].ready), // : out -- REG IF

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[verible-verilog-lint] hw/carfield.sv#L2523 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2523 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.AUEND_SDU (1'b0), // : in -- Connetti a '0'
.AUR_SDU (1'b0), // : in -- Connetti a '0'
.BIT_LOCKn (3'b0), // : in -- Connetti a '0'
.BUFFER_BUSY_SET (1'b0), // : in -- Da pilotare per mandare HPC/LLC dopo averli scritti in APB

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[verible-verilog-lint] hw/carfield.sv#L2527 

Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2527 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.CLCW_C_B (1'b0), // : in -- Connetti a '0'
.CLCW_S_B (1'b0), // : in -- Connetti a '0'
.CONF_REG_ACC_ACK (1'b1), // : in -- Era un'interfaccia interna che ora va semplificata, connetti a '1'

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[verible-verilog-lint] hw/carfield.sv#L2530 

Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2530 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.CPDU_INPROGRESS (1'b0), // : in -- Connetti a '0'
.EXT_OBT_CLK (1'b0), // : in -- Pin previsto per l'ASIC finale, ora lascia pure a '0'

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[verible-verilog-lint] hw/carfield.sv#L2532 

Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2532 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.HPC_LLC_CTRL_REG (32'b0), // : in -- Da pilotare, valore costante
.INT_PPS_IN (1'b0), // : in -- Pin previsto per l'ASIC finale, ora lascia pure a '0'

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[verible-verilog-lint] hw/carfield.sv#L2534 

Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2534 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.RFAVN (1'b0), // : in -- Connetti a '0'
.SDU_WRONG_LENGTH (1'b0), // : in -- Connetti a '0'
.SYNC_RST_N (1'b1), // : in -- Reset sincrono col sys_clk
.TC_ACTIVE (1'b0), // : in -- TC interface, pin dell'ASIC
.TC_CLOCK (1'b0), // : in -- TC interface, pin dell'ASIC
.TC_DATA (1'b0), // : in -- TC interface, pin dell'ASIC
.TME_CLCW_FSR_DAT_FROM_REM_PDEC_SEC (1'b0), // : in -- Connetti a '0'
.TME_ENCR_UNENC_CLK (1'b0), // : in -- Connetti a '0'
.TME_ENCR_UNENC_OUT (1'b0), // : in -- Connetti a '0'
.TME_ENCR_UNENC_SYNC (1'b0), // : in -- Connetti a '0'
.TME_FSR_DAT_FROM_LOC_SEC (1'b0), // : in -- Connetti a '0'
.ANACOND_LLC_RESET (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2546 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2546 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.AUTH_SEL (/* Not Connected */), // : out -- Lascia open
.BUSY (/* Not Connected */), // : out -- Da usare come info per mandare HPC/LLC dopo

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[verible-verilog-lint] hw/carfield.sv#L2548 

Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2548 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
// averli scritti in APB, al momento lascia pure open
.CADUFrameMark (/* Not Connected */), // : out -- Lascia open
.CLCWD_B (/* Not Connected */), // : out -- Lascia open
.CONF_REG_ACC_REQ (/* Not Connected */), // : out -- Era un'interfaccia interna che ora va semplificata,

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[verible-verilog-lint] hw/carfield.sv#L2552 

Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2552 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
// lascia open
.CONF_REG_ADDR_OFFSET (/* Not Connected */), // : out -- Era un'interfaccia interna che ora va semplificata,

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[verible-verilog-lint] hw/carfield.sv#L2554 

Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2554 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
// lascia open
.CONF_REG_GROUP_ADDR (/* Not Connected */), // : out -- Era un'interfaccia interna che ora va semplificata,

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[verible-verilog-lint] hw/carfield.sv#L2556 

Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2556 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
// lascia open
.CONF_REG_WDATA (/* Not Connected */), // : out -- Era un'interfaccia interna che ora va semplificata,

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[verible-verilog-lint] hw/carfield.sv#L2558 

Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 128 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2558 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
// lascia open
.CROSSED_LCL_RESET (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2560 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2560 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.CROSSED_POWER_REARM_OUT (/* Not Connected */), // : out -- Lascia open
.CROSSED_RESET_OUT (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2562 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2562 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.FPEMO (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2563 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2563 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.FPRELM (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2564 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2564 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.HPC_ADDR (/* Not Connected */), // : out -- ASIC out pin, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2565 

Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2565 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.HPC_CMD_EN (/* Not Connected */), // : out -- ASIC out pin, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2566 

Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2566 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.HPC_INTERRUPT_SOURCES (/* Not Connected */), // : out -- Collezione di interrupt, lascia open

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[verible-verilog-lint] hw/carfield.sv#L2567 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2567 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.HPC_PROTECTIONn (/* Not Connected */), // : out -- ASIC out pin, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2568 

Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2568 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.HPC_SMP (/* Not Connected */), // : out -- ASIC out pin, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2569 

Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2569 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.INH_MMA (/* Not Connected */), // : out -- Lascia open
.LLC_INTERRUPT_SOURCES (/* Not Connected */), // : out -- Collezione di interrupt, lascia open

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[verible-verilog-lint] hw/carfield.sv#L2571 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2571 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.LLC_IRQ_FORCE_REGISTER (/* Not Connected */), // : out -- Lascia open
.LOC_AOCS_LCL_PRI_BUS_ON_OFFn (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2573 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2573 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.LOC_AOCS_ON_OFFn (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2574 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2574 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.LOC_HK_ON_OFFn (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

Check warning on line 2575 in hw/carfield.sv

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[verible-verilog-lint] hw/carfield.sv#L2575 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2575 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.LOC_IO_ON_OFFn (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

Check warning on line 2576 in hw/carfield.sv

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[verible-verilog-lint] hw/carfield.sv#L2576 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2576 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.LOC_MCPM_ON_OFFn (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

Check warning on line 2577 in hw/carfield.sv

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[verible-verilog-lint] hw/carfield.sv#L2577 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2577 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.LOC_MCPM_RESET (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2578 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2578 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.LVDS_IF_TME_ENC_IOUT (/* Not Connected */), // : out -- Lascia open
.LVDS_IF_TME_ENC_IQCLK (/* Not Connected */), // : out -- Lascia open
.LVDS_IF_TME_ENC_QOUT (/* Not Connected */), // : out -- Lascia open
.PP0Busy_N (/* Not Connected */), // : out -- Lascia open
.PP1Busy_N (/* Not Connected */), // : out -- Lascia open
.PP2Busy_N (/* Not Connected */), // : out -- Lascia open
.PP3Busy_N (/* Not Connected */), // : out -- Lascia open
.PP4Busy_N (/* Not Connected */), // : out -- Lascia open
.PP5Busy_N (/* Not Connected */), // : out -- Lascia open
.PP6Busy_N (/* Not Connected */), // : out -- Lascia open
.PPS_OUT (/* Not Connected */), // : out -- Pin previsto per l'ASIC finale, ora lascia pure open

Check warning on line 2589 in hw/carfield.sv

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[verible-verilog-lint] hw/carfield.sv#L2589 

Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2589 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.REM_AOCS_LCL_PRI_BUS_ON_OFFn (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

Check warning on line 2590 in hw/carfield.sv

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[verible-verilog-lint] hw/carfield.sv#L2590 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2590 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.REM_AOCS_ON_OFFn (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

Check warning on line 2591 in hw/carfield.sv

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[verible-verilog-lint] hw/carfield.sv#L2591 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2591 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.REM_HK_ON_OFFn (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

Check warning on line 2592 in hw/carfield.sv

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[verible-verilog-lint] hw/carfield.sv#L2592 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2592 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.REM_IO_ON_OFFn (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

Check warning on line 2593 in hw/carfield.sv

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/carfield.sv#L2593 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2593 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.REM_MCPM_ON_OFFn (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2594 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2594 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.RM_RECOVERY_RESET (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2595 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2595 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.RM_RESET (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2596 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2596 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.RS422_IF_TME_ENC_CLK (/* Not Connected */), // : out -- Connetti a ASIC pin
.RS422_IF_TME_ENC_OUT (/* Not Connected */), // : out -- Connetti a ASIC pin
.RS422_IF_TME_ENC_SYNC (/* Not Connected */), // : out -- Connetti a ASIC pin
.SYNC_TO_EXT_IF (/* Not Connected */), // : out -- Pin previsto per l'ASIC finale, ora lascia pure open

Check warning on line 2600 in hw/carfield.sv

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/carfield.sv#L2600 

Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2600 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.TC_ONDOING (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/carfield.sv#L2601 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2601 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.TC_STANDARD (/* Not Connected */), // : out -- IF da semplificare, lascia pure open

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[verible-verilog-lint] hw/carfield.sv#L2602 

Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/carfield.sv" range:{start:{line:2602 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.TME_CLR_UNENC_CLK (/* Not Connected */), // : out -- Lascia open
.TME_CLR_UNENC_EODF_TO_ADAM (/* Not Connected */), // : out -- Lascia open
.TME_CLR_UNENC_EODF_TO_EXT (/* Not Connected */), // : out -- Lascia open
.TME_CLR_UNENC_OUT (/* Not Connected */), // : out -- Lascia open
.TME_CLR_UNENC_SYNC (/* Not Connected */), // : out -- Lascia open
.TME_Cn_S (/* Not Connected */), // : out -- Lascia open
.TME_REM_CLCWn_FSR_SEL (/* Not Connected */), // : out -- Lascia open
.TME_TIME_STROBE_TO_REM_OBT (/* Not Connected */), // : out -- Lascia open
.TME_UNENC_SYNC (/* Not Connected */) // : out -- Lascia open
);
assign ext_reg_async_slv_data_in[StreamerAsyncIdx].error = '0;
end else begin: gen_no_streamer
end
end else begin: gen_no_periph
assign car_regs_hw2reg.periph_isolate_status.d = '0;
assign car_regs_hw2reg.periph_isolate_status.de = '0;
Expand Down
22 changes: 19 additions & 3 deletions hw/carfield_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -211,13 +211,15 @@ typedef struct packed {
islands_properties_t pll;
islands_properties_t padframe;
islands_properties_t l2ecc;
islands_properties_t streamer;
} regbus_cfg_t;

typedef struct packed {
byte_bt pcrs;
byte_bt pll;
byte_bt padframe;
byte_bt l2ecc;
byte_bt streamer;
} carfield_regbus_slave_idx_t;

// Generate the number of AXI slave devices to be connected to the
Expand All @@ -233,14 +235,16 @@ function automatic int unsigned gen_num_regbus_async_slave(regbus_cfg_t regbus_c
if (regbus_cfg.pll.enable ) begin ret++; end
if (regbus_cfg.padframe.enable) begin ret++; end
if (regbus_cfg.l2ecc.enable ) begin ret++; end
if (regbus_cfg.streamer.enable) begin ret++; end
return ret;
endfunction

localparam regbus_cfg_t CarfieldRegBusCfg = '{
pcrs: '{1, PcrsBase, PcrsSize},
pll: '{PllCfgEnable, PllCfgBase, PllCfgSize},
padframe: '{PadframeCfgEnable, PadframeCfgBase, PadframeCfgSize},
l2ecc: '{L2EccCfgEnable, L2EccCfgBase, L2EccCfgSize}
l2ecc: '{L2EccCfgEnable, L2EccCfgBase, L2EccCfgSize},
streamer: '{StreamerCfgEnable, StreamerCfgBase, StreamerCfgSize}
};

localparam int unsigned NumSyncRegSlv = gen_num_regbus_sync_slave(CarfieldRegBusCfg);
Expand All @@ -262,6 +266,8 @@ function automatic carfield_regbus_slave_idx_t carfield_gen_regbus_slave_idx(reg
end else begin ret.padframe = NumTotalRegSlv + j; j++; end
if (regbus_cfg.l2ecc.enable) begin ret.l2ecc = i; i++;
end else begin ret.l2ecc = NumTotalRegSlv + j; j++; end
if (regbus_cfg.streamer.enable) begin ret.streamer = i; i++;
end else begin ret.streamer = NumTotalRegSlv + j; j++; end
return ret;
endfunction

Expand Down Expand Up @@ -301,6 +307,12 @@ function automatic regbus_struct_t carfield_gen_regbus_map(int unsigned NumSlave
ret.RegBusEnd[i] = regbus_cfg.l2ecc.base + regbus_cfg.l2ecc.size;
if (i < NumSlave - 1) i++;
end
if (regbus_cfg.streamer.enable) begin
ret.RegBusIdx[i] = idx.streamer;
ret.RegBusStart[i] = regbus_cfg.streamer.base;
ret.RegBusEnd[i] = regbus_cfg.streamer.base + regbus_cfg.streamer.size;
if (i < NumSlave - 1) i++;
end
return ret;
endfunction

Expand Down Expand Up @@ -709,7 +721,8 @@ typedef enum int {
AdvancedTimerIdx = 'd1,
SystemWdtIdx = 'd2,
CanIdx = 'd3,
HyperBusIdx = 'd4
HyperBusIdx = 'd4,
StreamerIdx = 'd5
} carfield_peripherals_e;

// Address map of peripheral system
Expand All @@ -734,7 +747,10 @@ localparam carfield_addr_map_rule_t [NumApbMst-1:0] PeriphApbAddrMapRule = '{
end_addr: CanBase + CanSize },
// 4: Hyperbus
'{ idx: HyperBusIdx, start_addr: HyperBusBase,
end_addr: HyperBusBase + HyperBusSize }
end_addr: HyperBusBase + HyperBusSize },
// 5: Streamer
'{ idx: StreamerIdx, start_addr: StreamerApbBase,
end_addr: StreamerApbBase + StreamerApbSize }
};

// Narrow reg types
Expand Down
95 changes: 95 additions & 0 deletions hw/configs/carfield_l2dual_secure_pulp_periph_can_streamer.sv
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,95 @@
// Copyright 2022 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
//
// Yvan Tortorella <[email protected]>

package carfield_configuration;

import cheshire_pkg::*;
/*********************
* AXI Configuration *
********************/
//L2, port 0
localparam bit L2Port0Enable = 1;
localparam doub_bt L2Port0Base = 'h78000000;
localparam doub_bt L2Port0Size = 'h00200000;
// L2, port 1
localparam bit L2Port1Enable = 1;
localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size;
localparam doub_bt L2Port1Size = L2Port0Size;
// Safety Island
localparam bit SafetyIslandEnable = 0;
localparam doub_bt SafetyIslandBase = 'h60000000;
localparam doub_bt SafetyIslandSize = 'h00800000;
// Ethernet
localparam bit EthernetEnable = 0;
localparam doub_bt EthernetBase = 'h20000000;
localparam doub_bt EthernetSize = 'h00001000;
// Peripherals
localparam bit PeriphEnable = 1;
localparam doub_bt PeriphBase = 'h20001000;
localparam doub_bt PeriphSize = 'h00009000;
// Spatz cluster
localparam bit SpatzClusterEnable = 0;
localparam doub_bt SpatzClusterBase = 'h51000000;
localparam doub_bt SpatzClusterSize = 'h00800000;
// PULP cluster
localparam bit PulpClusterEnable = 1;
localparam doub_bt PulpClusterBase = 'h50000000;
localparam doub_bt PulpClusterSize = 'h00800000;
// Security Island
localparam bit SecurityIslandEnable = 1;
localparam doub_bt SecurityIslandBase = 'h0;
localparam doub_bt SecurityIslandSize = 'h0;
// Mailbox
localparam bit MailboxEnable = 1;
localparam doub_bt MailboxBase = 'h40000000;
localparam doub_bt MailboxSize = 'h00001000;
/*********************
* APB Configuration *
********************/
// Can
localparam bit CanEnable = 1;
localparam doub_bt CanBase = 'h20001000;
localparam doub_bt CanSize = 'h00001000;
// Streamer
localparam bit StreamerEnable = 1;
localparam doub_bt StreamerApbBase = 'h20029000;
localparam doub_bt StreamerApbSize = 'h00008000;
// System Timer
localparam doub_bt SystemTimerBase = 'h20004000;
localparam doub_bt SystemTimerSize = 'h00001000;
// System Advanced Timer
localparam doub_bt SystemAdvancedTimerBase = 'h20005000;
localparam doub_bt SystemAdvancedTimerSize = 'h00001000;
// System Watchdog
localparam doub_bt SystemWatchdogBase = 'h20007000;
localparam doub_bt SystemWatchdogSize = 'h00001000;
// Hyperbus Config
localparam doub_bt HyperBusBase = 'h20009000;
localparam doub_bt HyperBusSize = 'h00001000;
/************************
* RegBus Configuration *
***********************/
// Platform control registers
localparam doub_bt PcrsBase = 'h20010000;
localparam doub_bt PcrsSize = 'h00001000;
// PLL
localparam bit PllCfgEnable = 1;
localparam doub_bt PllCfgBase = 'h20020000;
localparam doub_bt PllCfgSize = 'h00001000;
// Padframe
localparam bit PadframeCfgEnable = 1;
localparam doub_bt PadframeCfgBase = 'h200A0000;
localparam doub_bt PadframeCfgSize = 'h00001000;
// L2 ECC
localparam bit L2EccCfgEnable = 1;
localparam doub_bt L2EccCfgBase = 'h200B0000;
localparam doub_bt L2EccCfgSize = 'h00001000;
// Streamer
localparam bit StreamerCfgEnable = StreamerEnable;
localparam doub_bt StreamerCfgBase = 'h20021000;
localparam doub_bt StreamerCfgSize = 'h00008000;

endpackage
1 change: 1 addition & 0 deletions target/sim/sim.mk
View file
Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,7 @@ endif
$(CAR_VSIM_DIR)/compile.carfield_soc.tcl:
$(BENDER) script vsim $(common_targs) $(sim_targs) $(sim_defs) $(common_defs) $(safed_defs) --vlog-arg="$(RUNTIME_DEFINES)" --compilation-mode separate > $@
sed -i '2a\
set VsimDir "$(CAR_VSIM_DIR)"\
set TCTMPATH "$(STREAMER_ROOT)"\
source $(STREAMER_ROOT)/astral.compile.tcl' $@
echo 'vlog "$(CHS_ROOT)/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@
Expand Down

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