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Feature/improve unit tests coverage #189

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1824b93
Added more unit tests for poly
rutefig Dec 25, 2023
2e726a2
Added more unit tests for ast/query
rutefig Dec 25, 2023
c831c88
Formatting fixes
rutefig Dec 25, 2023
7483dd3
Added more unit tests for dsl/mod
rutefig Dec 27, 2023
5c96d01
Added unit tests for Constraint on dsl::cb
rutefig Dec 29, 2023
66661e2
Added more unit tests for compiler/step_selector
rutefig Jan 8, 2024
e9340b9
Added more unit tests for compiler
rutefig Jan 11, 2024
4dd470b
fixed some mistakes
rutefig Jan 11, 2024
cd68d49
Added unit tests for Super Circuit
rutefig Jan 13, 2024
82ade6b
fix formatting and clippy
rutefig Jan 14, 2024
0cbe7d5
fixes from PR review
rutefig Jan 20, 2024
6198b55
Merge branch 'main' into feature/improve-unit-tests-coverage
rutefig Jan 23, 2024
de43768
fixed tests failing after merge conflicts
rutefig Jan 23, 2024
3844c33
ignore test for compile_phase2 before flagging compilation phases not…
rutefig Jan 29, 2024
f170e35
ignore test when exposing a non existing signal - waiting for check t…
rutefig Jan 29, 2024
df720ac
Merge branch 'main' into feature/improve-unit-tests-coverage
rutefig Feb 29, 2024
86fe3e5
improved some tests on plonkish::ir::sc
rutefig Mar 4, 2024
b274c59
fixed mistakes for poly
rutefig Mar 4, 2024
f8db6ac
formatting
rutefig Mar 4, 2024
c131714
removed wrong tests for query
rutefig Mar 4, 2024
bfe9fd2
Merge branch 'main' into feature/improve-unit-tests-coverage
rutefig Mar 4, 2024
f860065
formatting
rutefig Mar 4, 2024
25e4578
Merge branch 'feature/improve-unit-tests-coverage' of github.com:rute…
rutefig Mar 4, 2024
4a64cac
ignore pointer and use default debug for sc
rutefig Mar 18, 2024
8ad9cc0
improved tests on frontend::dsl::sc
rutefig Mar 20, 2024
c4234b3
test sub circuit with ast for super circuit frontend
rutefig Mar 20, 2024
9d9fcb8
refactor for poly and fixed some scopes on sc
rutefig Mar 21, 2024
31cf4a8
formatting
rutefig Mar 21, 2024
8be82d7
Merge branch 'main' into feature/improve-unit-tests-coverage
rutefig Mar 21, 2024
4fb0b66
clippy fix
rutefig Mar 21, 2024
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47 changes: 47 additions & 0 deletions src/frontend/dsl/cb.rs
Original file line number Diff line number Diff line change
Expand Up @@ -716,4 +716,51 @@ mod tests {
matches!(v[1], Expr::Const(c) if c == 40u64.field())) &&
matches!(v[1], Expr::Const(c) if c == 10u64.field())));
}

#[test]
fn test_constraint_from_queriable() {
// Create a Queriable instance and convert it to a Constraint
let queriable = Queriable::StepTypeNext(StepTypeHandler::new("test_step".to_owned()));
let constraint: Constraint<Fr> = Constraint::from(queriable);

assert_eq!(constraint.annotation, "test_step");
assert!(
matches!(constraint.expr, Expr::Query(Queriable::StepTypeNext(s)) if
matches!(s, StepTypeHandler {id: _id, annotation: "test_step"}))
);
assert!(matches!(constraint.typing, Typing::Boolean));
}

#[test]
fn test_constraint_from_expr() {
// Create an expression and convert it to a Constraint
let expr = <u64 as ToExpr<Fr, Queriable<Fr>>>::expr(&10) * 20u64.expr();
let constraint: Constraint<Fr> = Constraint::from(expr);

// returns "10 * 20"
assert!(matches!(constraint.expr, Expr::Mul(v) if v.len() == 2 &&
matches!(v[0], Expr::Const(c) if c == 10u64.field()) &&
matches!(v[1], Expr::Const(c) if c == 20u64.field())));
assert!(matches!(constraint.typing, Typing::Unknown));
}

#[test]
fn test_constraint_from_int() {
// Create an integer and convert it to a Constraint
let constraint: Constraint<Fr> = Constraint::from(10);

// returns "10"
assert!(matches!(constraint.expr, Expr::Const(c) if c == 10u64.field()));
assert!(matches!(constraint.typing, Typing::Unknown));
}

#[test]
fn test_constraint_from_bool() {
// Create a boolean and convert it to a Constraint
let constraint: Constraint<Fr> = Constraint::from(true);

assert_eq!(constraint.annotation, "0x1");
assert!(matches!(constraint.expr, Expr::Const(c) if c == 1u64.field()));
assert!(matches!(constraint.typing, Typing::Unknown));
}
}
173 changes: 108 additions & 65 deletions src/frontend/dsl/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -154,6 +154,8 @@ impl<F, TraceArgs> CircuitContext<F, TraceArgs> {
self.circuit.last_step = Some(step_type.into().uuid());
}

/// Enforce the number of step instances by adding a constraint to the circuit. Takes a `usize`
/// parameter that represents the total number of steps.
pub fn pragma_num_steps(&mut self, num_steps: usize) {
self.circuit.num_steps = num_steps;
}
Expand Down Expand Up @@ -225,6 +227,7 @@ impl<F> StepTypeContext<F> {
}

/// DEPRECATED
// #[deprecated(note = "use step types setup for constraints instead")]
pub fn constr<C: Into<Constraint<F>>>(&mut self, constraint: C) {
println!("DEPRECATED constr: use setup for constraints in step types");

Expand All @@ -235,6 +238,7 @@ impl<F> StepTypeContext<F> {
}

/// DEPRECATED
#[deprecated(note = "use step types setup for constraints instead")]
pub fn transition<C: Into<Constraint<F>>>(&mut self, constraint: C) {
println!("DEPRECATED transition: use setup for constraints in step types");

Expand Down Expand Up @@ -424,28 +428,49 @@ pub mod sc;

#[cfg(test)]
mod tests {
use crate::sbpir::ForwardSignal;

use super::*;

fn setup_circuit_context<F, TraceArgs>() -> CircuitContext<F, TraceArgs>
where
F: Default,
TraceArgs: Default,
{
CircuitContext {
circuit: SBPIR::default(),
tables: Default::default(),
}
}

#[test]
fn test_disable_q_enable() {
fn test_circuit_default_initialization() {
let circuit: SBPIR<i32, i32> = SBPIR::default();
let mut context = CircuitContext {
circuit,
tables: Default::default(),
};

context.pragma_disable_q_enable();
// Assert default values
assert!(circuit.step_types.is_empty());
assert!(circuit.forward_signals.is_empty());
assert!(circuit.shared_signals.is_empty());
assert!(circuit.fixed_signals.is_empty());
assert!(circuit.exposed.is_empty());
assert!(circuit.annotations.is_empty());
assert!(circuit.trace.is_none());
assert!(circuit.first_step.is_none());
assert!(circuit.last_step.is_none());
assert!(circuit.num_steps == 0);
assert!(circuit.q_enable);
}

#[test]
fn test_disable_q_enable() {
let mut context = setup_circuit_context::<i32, i32>();
context.pragma_disable_q_enable();
assert!(!context.circuit.q_enable);
}

#[test]
fn test_set_num_steps() {
let circuit: SBPIR<i32, i32> = SBPIR::default();
let mut context = CircuitContext {
circuit,
tables: Default::default(),
};
let mut context = setup_circuit_context::<i32, i32>();

context.pragma_num_steps(3);
assert_eq!(context.circuit.num_steps, 3);
Expand All @@ -454,14 +479,29 @@ mod tests {
assert_eq!(context.circuit.num_steps, 0);
}

#[test]
fn test_set_first_step() {
let mut context = setup_circuit_context::<i32, i32>();

let step_type: StepTypeHandler = context.step_type("step_type");

context.pragma_first_step(step_type);
assert_eq!(context.circuit.first_step, Some(step_type.uuid()));
}

#[test]
fn test_set_last_step() {
let mut context = setup_circuit_context::<i32, i32>();

let step_type: StepTypeHandler = context.step_type("step_type");

context.pragma_last_step(step_type);
assert_eq!(context.circuit.last_step, Some(step_type.uuid()));
}

#[test]
fn test_forward() {
// create circuit context
let circuit: SBPIR<i32, i32> = SBPIR::default();
let mut context = CircuitContext {
circuit,
tables: Default::default(),
};
let mut context = setup_circuit_context::<i32, i32>();

// set forward signals
let forward_a: Queriable<i32> = context.forward("forward_a");
Expand All @@ -473,14 +513,21 @@ mod tests {
assert_eq!(context.circuit.forward_signals[1].uuid(), forward_b.uuid());
}

#[test]
fn test_adding_duplicate_signal_names() {
let mut context = setup_circuit_context::<i32, i32>();
context.forward("duplicate_name");
context.forward("duplicate_name");
// Assert how the system should behave. Does it override the previous signal, throw an
// error, or something else?
// TODO: Should we let the user know that they are adding a duplicate signal name? And let
// the circuit have two signals with the same name?
assert_eq!(context.circuit.forward_signals.len(), 2);
}

#[test]
fn test_forward_with_phase() {
// create circuit context
let circuit: SBPIR<i32, i32> = SBPIR::default();
let mut context = CircuitContext {
circuit,
tables: Default::default(),
};
let mut context = setup_circuit_context::<i32, i32>();

// set forward signals with specified phase
context.forward_with_phase("forward_a", 1);
Expand All @@ -494,12 +541,7 @@ mod tests {

#[test]
fn test_shared() {
// create circuit context
let circuit: SBPIR<i32, i32> = SBPIR::default();
let mut context = CircuitContext {
circuit,
tables: Default::default(),
};
let mut context = setup_circuit_context::<i32, i32>();

// set shared signal
let shared_a: Queriable<i32> = context.shared("shared_a");
Expand All @@ -511,12 +553,7 @@ mod tests {

#[test]
fn test_shared_with_phase() {
// create circuit context
let circuit: SBPIR<i32, i32> = SBPIR::default();
let mut context = CircuitContext {
circuit,
tables: Default::default(),
};
let mut context = setup_circuit_context::<i32, i32>();

// set shared signal with specified phase
context.shared_with_phase("shared_a", 2);
Expand All @@ -528,12 +565,7 @@ mod tests {

#[test]
fn test_fixed() {
// create circuit context
let circuit: SBPIR<i32, i32> = SBPIR::default();
let mut context = CircuitContext {
circuit,
tables: Default::default(),
};
let mut context = setup_circuit_context::<i32, i32>();

// set fixed signal
context.fixed("fixed_a");
Expand All @@ -544,12 +576,7 @@ mod tests {

#[test]
fn test_expose() {
// create circuit context
let circuit: SBPIR<i32, i32> = SBPIR::default();
let mut context = CircuitContext {
circuit,
tables: Default::default(),
};
let mut context = setup_circuit_context::<i32, i32>();

// set forward signal and step to expose
let forward_a: Queriable<i32> = context.forward("forward_a");
Expand All @@ -566,14 +593,21 @@ mod tests {
);
}

#[test]
#[ignore]
#[should_panic(expected = "Signal not found")]
fn test_expose_non_existing_signal() {
let mut context = setup_circuit_context::<i32, i32>();
let non_existing_signal =
Queriable::Forward(ForwardSignal::new_with_phase(0, "".to_owned()), false); // Create a signal not added to the circuit
context.expose(non_existing_signal, ExposeOffset::First);

todo!("remove the ignore after fixing the check for non existing signals")
}

#[test]
fn test_step_type() {
// create circuit context
let circuit: SBPIR<i32, i32> = SBPIR::default();
let mut context = CircuitContext {
circuit,
tables: Default::default(),
};
let mut context = setup_circuit_context::<i32, i32>();

// create a step type
let handler: StepTypeHandler = context.step_type("fibo_first_step");
Expand All @@ -587,12 +621,7 @@ mod tests {

#[test]
fn test_step_type_def() {
// create circuit context
let circuit: SBPIR<i32, i32> = SBPIR::default();
let mut context = CircuitContext {
circuit,
tables: Default::default(),
};
let mut context = setup_circuit_context::<i32, i32>();

// create a step type including its definition
let simple_step = context.step_type_def("simple_step", |context| {
Expand All @@ -613,12 +642,7 @@ mod tests {

#[test]
fn test_step_type_def_pass_handler() {
// create circuit context
let circuit: SBPIR<i32, i32> = SBPIR::default();
let mut context = CircuitContext {
circuit,
tables: Default::default(),
};
let mut context = setup_circuit_context::<i32, i32>();

// create a step type handler
let handler: StepTypeHandler = context.step_type("simple_step");
Expand All @@ -639,4 +663,23 @@ mod tests {
context.circuit.step_types[&simple_step.uuid()].uuid()
);
}

#[test]
fn test_trace() {
let mut context = setup_circuit_context::<i32, i32>();

// set trace function
context.trace(|_, _: i32| {});

// assert trace function was set
assert!(context.circuit.trace.is_some());
}

#[test]
#[should_panic(expected = "circuit cannot have more than one trace generator")]
fn test_setting_trace_multiple_times() {
let mut context = setup_circuit_context::<i32, i32>();
context.trace(|_, _| {});
context.trace(|_, _| {});
}
}
50 changes: 50 additions & 0 deletions src/frontend/dsl/sc.rs
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@ use crate::{

use super::{lb::LookupTableRegistry, CircuitContext};

#[derive(Debug)]
pub struct SuperCircuitContext<F, MappingArgs> {
super_circuit: SuperCircuit<F, MappingArgs>,
sub_circuit_phase1: Vec<CompilationUnit<F>>,
Expand Down Expand Up @@ -120,3 +121,52 @@ where

ctx.compile()
}

#[cfg(test)]
mod tests {
use halo2curves::bn256::Fr;

use crate::plonkish::compiler::{
cell_manager::SingleRowCellManager, config, step_selector::SimpleStepSelectorBuilder,
};

use super::*;

#[test]
fn test_super_circuit_context_default() {
let ctx = SuperCircuitContext::<Fr, ()>::default();

assert_eq!(
format!("{:#?}", ctx.super_circuit),
format!("{:#?}", SuperCircuit::<Fr, ()>::default())
);
assert_eq!(
format!("{:#?}", ctx.sub_circuit_phase1),
format!("{:#?}", Vec::<CompilationUnit<Fr>>::default())
);
assert_eq!(ctx.sub_circuit_phase1.len(), 0);
assert_eq!(
format!("{:#?}", ctx.tables),
format!("{:#?}", LookupTableRegistry::<Fr>::default())
);
}

#[test]
fn test_super_circuit_context_sub_circuit() {
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let mut ctx = SuperCircuitContext::<Fr, ()>::default();

let (_, _) = ctx.sub_circuit(
config(
SingleRowCellManager::default(),
SimpleStepSelectorBuilder::default(),
),
|ctx: &mut CircuitContext<Fr, ()>, _| {
ctx.fixed("fixed signal");
},
(),
);

assert_eq!(ctx.sub_circuit_phase1.len(), 1);
assert_eq!(ctx.sub_circuit_phase1[0].columns.len(), 2);
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}
}
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