Merge pull request #157 from physical-computation/Issue#155,-using-bi…

…t-masking Issue#155, using bit masking
physical-computation · Apr 7, 2020 · 587e3ad · 587e3ad
2 parents 4c91f4f + 430762b
commit 587e3ad
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Showing 2 changed files with 16 additions and 8 deletions.
diff --git a/sim/bit.h b/sim/bit.h
@@ -134,15 +134,18 @@ enum
  maskExtractBit7 = 0x1 << 7,
  maskExtractBits7to11 = 0x1F << 7,
  maskExtractBits8to11 = 0xF << 8,
+ maskExtractBits12to14 = 0x7 << 12,
  maskExtractBits12to19 = 0xFF << 12,
  maskExtractBits12to31 = 0xFFFFF << 12,
  maskExtractBits15to19 = 0x1F << 15,
  maskExtractBit20 = 0x1 << 20,
  maskExtractBits20to24 = 0x1F << 20,
  maskExtractBits20to31 = 0xFFF << 20,
  maskExtractBits21to30 = 0x7FE << 20,
+ maskExtractBits25to26 = 0x3 << 25,
  maskExtractBits25to30 = 0x3F << 25,
  maskExtractBits25to31 = 0x7F << 25,
+ maskExtractBits27to31 = 0x1F << 27,
  maskExtractBit31 = 0x1 << 31,
 
 };

diff --git a/sim/pipeline-riscv.c b/sim/pipeline-riscv.c
@@ -95,7 +95,7 @@ Assumed pipeline implementation:
  1 stall:
  LOAD instrs that write to a reg-required-by-next-instr after reading from mem:
  ...EX of next instr needs reg data from MA of LOAD instrs.
- BRANCH instrs test for (in)equality in ID, dependent on previous instr:
+ BRANCH instrs test for (in)equality in ID which is dependent on previous instr:
  ...ID of BRANCH instr needs reg data from EX of previous instr.
  2 stalls:
  LOAD instr followed by dependent BRANCH instr:
@@ -634,17 +634,23 @@ riscvstep(Engine *E, State *S, int drain_pipeline)
  (tmp&maskExtractBit20) >> 20,
  (tmp&maskExtractBits12to19) >> 12,
  (tmp&maskExtractBit31) >> 31);
- S->dyncnt++; */
+ S->dyncnt++;
+ 
  S->riscv->instruction_distribution[S->riscv->P.EX.op]++;
+ */
+
  break;
  }
 
  case INSTR_R4:
  {
- instr_r4 *tmp;
-
- tmp = (instr_r4 *)&S->riscv->P.EX.instr;
- (*(S->riscv->P.EX.fptr))(E, S, tmp->rs1, tmp->rs2, tmp->rs3, tmp->rm, tmp->rd);
+ uint32_t tmp = S->riscv->P.EX.instr;
+ (*(S->riscv->P.EX.fptr))(E, S,
+ (tmp&maskExtractBits15to19) >> 15,
+ (tmp&maskExtractBits20to24) >> 20,
+ (tmp&maskExtractBits27to31) >> 27,
+ (tmp&maskExtractBits12to14) >> 12,
+ (tmp&maskExtractBits7to11) >> 7);
  break;
  }
 
@@ -750,7 +756,6 @@ riscvstep(Engine *E, State *S, int drain_pipeline)
  (tmp&maskExtractBit20) >> 20,
  (tmp&maskExtractBits12to19) >> 12,
  (tmp&maskExtractBit31) >> 31);
- S->riscv->instruction_distribution[S->riscv->P.ID.op]++;
  }
  else
  {
@@ -762,8 +767,8 @@ riscvstep(Engine *E, State *S, int drain_pipeline)
  (tmp&maskExtractBits25to30) >> 25,
  (tmp&maskExtractBit7) >> 7,
  (tmp&maskExtractBit31) >> 31);
- S->riscv->instruction_distribution[S->riscv->P.ID.op]++;
  }
+ S->riscv->instruction_distribution[S->riscv->P.ID.op]++;
  S->dyncnt++;
  riscvIFflush(S);
  }