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SamuelmsWong-zz authored Jan 18, 2020
1 parent a5dfd69 commit 430762b
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion sim/pipeline-riscv.c
Original file line number Diff line number Diff line change
Expand Up @@ -641,7 +641,7 @@ riscvstep(Engine *E, State *S, int drain_pipeline)

break;
}

case INSTR_R4:
{
uint32_t tmp = S->riscv->P.EX.instr;
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