Merge branch 'backend' of github.com:RapidSilicon/IP_Catalog into bac…

…kend
os-fpga · Oct 4, 2023 · 051aa20 · 051aa20
2 parents 8728326 + 2639300
commit 051aa20
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Showing 5 changed files with 41 additions and 3 deletions.
diff --git a/rapidsilicon/ip/axis_ram_switch/v1_0/axis_ram_switch_gen.py b/rapidsilicon/ip/axis_ram_switch/v1_0/axis_ram_switch_gen.py
@@ -245,9 +245,17 @@ def main():
 
     args = parser.parse_args()
 
+    details =  {   "IP details": {
+    'Name' : 'AXI-Stream RAM Switch',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI-Streaming',
+    'Description' : 'The AXIS RAM Switch core is an AXI4-Streaming compliant customizable switch that is designed to be used in applications that require configurable buffered routing between masters and slaves with multiple arbitration options.'}
+    }
+
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0")
         if(args.m_count):
             if (args.m_count == 1):
                 parser._actions[17].choices = range(1, 17)
@@ -262,9 +270,21 @@ def main():
                 parser._actions[18].choices = range(1, math.floor(31/args.s_count) + 1)
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
 
+    summary =  { 
+    "Master Data Width" : args.m_data_width,
+    "Slave Data Width" : args.s_data_width,
+    "FIFO Depth" : args.fifo_depth,
+    "RAM Pipeline stages" : args.ram_pipeline,
+    "Number of Masters" : args.m_count,
+    "Number of Slaves" : args.s_count,
+    "Masters base address offset" : args.m_base,
+    "Masters top address offset" : args.m_top,
+    "Speed Scale Factor" : args.speedup
+    }
+
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

diff --git a/rapidsilicon/ip/axis_ram_switch/v1_0/docs/axis_ram_switch_blackbox.png b/rapidsilicon/ip/axis_ram_switch/v1_0/docs/axis_ram_switch_blackbox.png
diff --git a/rapidsilicon/ip/axis_switch/v1_0/axis_switch_gen.py b/rapidsilicon/ip/axis_switch/v1_0/axis_switch_gen.py
@@ -216,9 +216,17 @@ def main():
 
     args = parser.parse_args()
 
+    details =  {   "IP details": {
+    'Name' : 'AXI-Stream Switch',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI-Streaming',
+    'Description' : 'The AXIS Switch core is an AXI4-Streaming compliant customizable switch that is designed to be used in applications that require configurable routing between masters and slaves with multiple arbitration options.'}
+    }
+
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0")
         if(args.m_count):
             if (args.m_count == 1):
                 parser._actions[12].choices = range(1, 17)
@@ -233,9 +241,19 @@ def main():
                 parser._actions[13].choices = range(1, math.floor(31/args.s_count) + 1)
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
 
+    summary =  { 
+    "Data Width" : args.data_width,
+    "Master Register Type" : args.m_reg_type,
+    "Slave Register Type" : args.s_reg_type,
+    "Number of Masters" : args.m_count,
+    "Number of Slaves" : args.s_count,
+    "Masters base address offset" : args.m_base,
+    "Masters top address offset" : args.m_top
+    }
+
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

diff --git a/rapidsilicon/ip/axis_switch/v1_0/docs/axis_switch_blackbox.png b/rapidsilicon/ip/axis_switch/v1_0/docs/axis_switch_blackbox.png
diff --git a/rapidsilicon/ip/vexriscv_cpu/v1_0/vexriscv_cpu_gen.py b/rapidsilicon/ip/vexriscv_cpu/v1_0/vexriscv_cpu_gen.py
@@ -287,7 +287,7 @@ def main():
     'Name' : 'VexRiscv_CPU',
     'Version' : 'V1_0',
     'Interface' : 'AXI',
-    'Description' : 'The VexRiscv CPU is a 32 bit, AXI4 compliant socomputations on FPGAs in the form of soft SoCs. It is a modern and complete soft processor that can be used to boot Operating Systems or used in a bare metal fashion.'}
+    'Description' : 'The VexRiscv CPU is a 32 bit, AXI4 compliant soft processor designed to be used in applications that require fast computations on FPGAs in the form of soft SoCs. It is a modern and complete soft processor that can be used to boot Operating Systems or used in a bare metal fashion.'}
     }
 
     # Import JSON (Optional) -----------------------------------------------------------------------