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ip details added for GUI
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@moinijaz-RS
moinijaz-RS committed Oct 4, 2023
1 parent 179e6f9 commit 8728326
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Showing 5 changed files with 127 additions and 30 deletions.
27 changes: 21 additions & 6 deletions rapidsilicon/ip/axi_dpram/v1_0/axi_dpram_gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
import sys
import logging
import argparse
import math

from datetime import datetime

Expand Down Expand Up @@ -103,18 +104,18 @@ def main():
core_fix_param_group = parser.add_argument_group(title="Core fix parameters")
core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[8, 16, 32, 64, 128, 256], help="DPRAM Data Width.")

# Core range value parameters.
core_range_param_group = parser.add_argument_group(title="Core range parameters")
core_range_param_group.add_argument("--addr_width", type=int, default=16, choices=range(8, 17), help="DPRAM Address Width.")
core_range_param_group.add_argument("--id_width", type=int, default=32, choices=range(1, 33), help="DPRAM ID Width.")

# Core bool value parameters.
core_bool_param_group = parser.add_argument_group(title="Core bool parameters")
core_bool_param_group.add_argument("--a_pip_out", type=bool, default=True, help="DPRAM A Pipeline Output.")
core_bool_param_group.add_argument("--b_pip_out", type=bool, default=True, help="DPRAM B Pipeline Output.")
core_bool_param_group.add_argument("--a_interleave", type=bool, default=True, help="DPRAM A Interleave.")
core_bool_param_group.add_argument("--b_interleave", type=bool, default=True, help="DPRAM B Interleave.")

# Core range value parameters.
core_range_param_group = parser.add_argument_group(title="Core range parameters")
core_range_param_group.add_argument("--addr_width", type=int, default=16, choices=range(8, 17), help="DPRAM Address Width.")
core_range_param_group.add_argument("--id_width", type=int, default=32, choices=range(1, 33), help="DPRAM ID Width.")

# Build Parameters.
build_group = parser.add_argument_group(title="Build parameters")
build_group.add_argument("--build", action="store_true", help="Build Core")
Expand All @@ -127,14 +128,28 @@ def main():
json_group.add_argument("--json-template", action="store_true", help="Generate JSON Template")

args = parser.parse_args()

details = { "IP details": {
'Name' : 'AXI DUAL-PORT RAM',
'Version' : 'V1_0',
'Interface' : 'AXI',
'Description' : 'AXI DUAL-PORT RAM is a AXI4 compliant IP Core. This IP Core provides two independent memory ports, each adhering to the Advanced eXtensible Interface (AXI) standard, making it ideal for applications that require simultaneous read and write access to memory. It simplifies the integration of dual-port memory into FPGA and SoC designs, ensuring fast and concurrent read and write operations for a wide range of applications, from high-speed data processing to real-time control systems.'}
}

# Import JSON (Optional) -----------------------------------------------------------------------
if args.json:
args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0")

summary = {
"DATA PORT": args.data_width,
"DEPTH": 2**(args.addr_width),
"MEMORY SIZE (KB)": math.ceil(((args.data_width * args.addr_width)/(8*1024))*100)
}

# Export JSON Template (Optional) --------------------------------------------------------------
if args.json_template:
rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)

# Create Wrapper -------------------------------------------------------------------------------
platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")
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46 changes: 36 additions & 10 deletions rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -113,14 +113,6 @@ def main():
core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[8, 16, 32, 64, 128, 256], help="AXI Data Width.")
core_fix_param_group.add_argument("--addr_width", type=int, default=32, choices=[32, 64, 128], help="AXI Address Width.")

# Core bool value parameters.
core_bool_param_group = parser.add_argument_group(title="Core bool parameters")
core_bool_param_group.add_argument("--aw_user_en", type=bool, default=True, help="AW-Channel User Enable.")
core_bool_param_group.add_argument("--w_user_en", type=bool, default=True, help="W-Channel User Enable.")
core_bool_param_group.add_argument("--b_user_en", type=bool, default=True, help="B-Channel User Enable.")
core_bool_param_group.add_argument("--ar_user_en", type=bool, default=True, help="AR-Channel User Enable.")
core_bool_param_group.add_argument("--r_user_en", type=bool, default=True, help="R-Channel User Enable.")

# Core range value parameters.
core_range_param_group = parser.add_argument_group(title="Core range parameters")
core_range_param_group.add_argument("--m_count", type=int, default=4, choices=range(1,17), help="Interconnect Master Interfaces.")
Expand All @@ -132,6 +124,14 @@ def main():
core_range_param_group.add_argument("--ar_user_width", type=int, default=1, choices=range(1, 1025), help="AR-Channel User Width.")
core_range_param_group.add_argument("--r_user_width", type=int, default=1, choices=range(1, 1025), help="R-Channel User Width.")

# Core bool value parameters.
core_bool_param_group = parser.add_argument_group(title="Core bool parameters")
core_bool_param_group.add_argument("--aw_user_en", type=bool, default=True, help="AW-Channel User Enable.")
core_bool_param_group.add_argument("--w_user_en", type=bool, default=True, help="W-Channel User Enable.")
core_bool_param_group.add_argument("--b_user_en", type=bool, default=True, help="B-Channel User Enable.")
core_bool_param_group.add_argument("--ar_user_en", type=bool, default=True, help="AR-Channel User Enable.")
core_bool_param_group.add_argument("--r_user_en", type=bool, default=True, help="R-Channel User Enable.")

# Build Parameters.
build_group = parser.add_argument_group(title="Build parameters")
build_group.add_argument("--build", action="store_true", help="Build Core")
Expand All @@ -144,14 +144,40 @@ def main():
json_group.add_argument("--json-template", action="store_true", help="Generate JSON Template")

args = parser.parse_args()

details = { "IP details": {
'Name' : 'AXI INTERCONNECT',
'Version' : 'V1_0',
'Interface' : 'AXI',
'Description' : 'AXI INTERCONNECT is a AXI4 compliant IP Core. This IP Core serves as a crucial bridge in FPGA and SoC designs, facilitating efficient and scalable communication between various components and peripherals. It acts as a central hub, connecting multiple AXI masters to AXI slaves within the system.'}
}

# Import JSON (Optional) -----------------------------------------------------------------------
if args.json:
args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)

rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0")

summary = {
"NUMBER OF MASTER INTERFACES": args.m_count,
"NUMBER OF SLAVE INTERFACES": args.s_count,
"AXI DATA PORT WIDTH": args.data_width,
"AXI ADDR PORT WIDTH": args.addr_width
# "ID WIDTH": args.id_width,
# "AW USER WIDTH": args.aw_user_width,
# "W USER WIDTH": args.w_user_width,
# "B USER WIDTH": args.b_user_width,
# "AR USER WIDTH": args.ar_user_width,
# "R USER WIDTH": args.r_user_width,
# "AW USER ENABLE": args.aw_user_en,
# "W USER ENABLE": args.w_user_en,
# "B USER ENABLE": args.b_user_en,
# "AR USER ENABLE": args.ar_user_en,
# "R USER ENABLE": args.r_user_en
}

# Export JSON Template (Optional) --------------------------------------------------------------
if args.json_template:
rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)

# Create Wrapper -------------------------------------------------------------------------------
platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")
Expand Down
20 changes: 18 additions & 2 deletions rapidsilicon/ip/axi_ram/v1_0/axi_ram_gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
import sys
import logging
import argparse
import math

from datetime import datetime

Expand Down Expand Up @@ -105,13 +106,28 @@ def main():

args = parser.parse_args()

details = { "IP details": {
'Name' : 'AXI RAM',
'Version' : 'V1_0',
'Interface' : 'AXI',
'Description' : 'AXI RAM is a AXI4 compliant IP Core. This IP Core can be tailored to meet specific memory size and bandwidth requirements, making it ideal for various embedded systems. Its reliability and scalability make it a valuable component for building efficient and high-performance FPGA and SoC-based designs.'}
}

# Import JSON (Optional) -----------------------------------------------------------------------
if args.json:
args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)

rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0")

summary = {
# "DATA WIDTH": args.data_width,
"DEPTH": 2**(args.addr_width),
"MEMORY SIZE (KB)": math.ceil(((args.data_width * args.addr_width)/(8*1024))*100)
# "PIPELINE OUTPUT": args.pip_out
}

# Export JSON Template (Optional) --------------------------------------------------------------
if args.json_template:
rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)

# Create Wrapper -------------------------------------------------------------------------------
platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")
Expand Down
45 changes: 35 additions & 10 deletions rapidsilicon/ip/axi_register/v1_0/axi_register_gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -108,14 +108,6 @@ def main():
logging.info("===================================================")
logging.info("IP : %s", rs_builder.ip_name.upper())
logging.info(("==================================================="))

# Core string parameters.
core_string_param_group = parser.add_argument_group(title="Core string parameters")
core_string_param_group.add_argument("--aw_reg_type", type=str, default="Simple_Buffer", choices=["Bypass", "Simple_Buffer", "Skid_Buffer"], help="Type of Register")
core_string_param_group.add_argument("--w_reg_type", type=str, default="Skid_Buffer", choices=["Bypass", "Simple_Buffer", "Skid_Buffer"], help="Type of Register")
core_string_param_group.add_argument("--b_reg_type", type=str, default="Simple_Buffer", choices=["Bypass", "Simple_Buffer", "Skid_Buffer"], help="Type of Register")
core_string_param_group.add_argument("--ar_reg_type", type=str, default="Simple_Buffer", choices=["Bypass", "Simple_Buffer", "Skid_Buffer"], help="Type of Register")
core_string_param_group.add_argument("--r_reg_type", type=str, default="Skid_Buffer", choices=["Bypass", "Simple_Buffer", "Skid_Buffer"], help="Type of Register")

# Core fix value parameters.
core_fix_param_group = parser.add_argument_group(title="Core fix parameters")
Expand All @@ -131,6 +123,14 @@ def main():
core_range_param_group.add_argument("--ar_user_width", type=int, default=1, choices=range(1, 1025), help="Register AR-User Width.")
core_range_param_group.add_argument("--r_user_width", type=int, default=1, choices=range(1, 1025), help="Register R-User Width.")

# Core string parameters.
core_string_param_group = parser.add_argument_group(title="Core string parameters")
core_string_param_group.add_argument("--aw_reg_type", type=str, default="Simple_Buffer", choices=["Bypass", "Simple_Buffer", "Skid_Buffer"], help="Type of Register")
core_string_param_group.add_argument("--w_reg_type", type=str, default="Skid_Buffer", choices=["Bypass", "Simple_Buffer", "Skid_Buffer"], help="Type of Register")
core_string_param_group.add_argument("--b_reg_type", type=str, default="Simple_Buffer", choices=["Bypass", "Simple_Buffer", "Skid_Buffer"], help="Type of Register")
core_string_param_group.add_argument("--ar_reg_type", type=str, default="Simple_Buffer", choices=["Bypass", "Simple_Buffer", "Skid_Buffer"], help="Type of Register")
core_string_param_group.add_argument("--r_reg_type", type=str, default="Skid_Buffer", choices=["Bypass", "Simple_Buffer", "Skid_Buffer"], help="Type of Register")

# Build Parameters.
build_group = parser.add_argument_group(title="Build parameters")
build_group.add_argument("--build", action="store_true", help="Build Core")
Expand All @@ -144,13 +144,38 @@ def main():

args = parser.parse_args()

details = { "IP details": {
'Name' : 'AXI REGISTER',
'Version' : 'V1_0',
'Interface' : 'AXI',
'Description' : 'AXI REGISTER is a AXI4 compliant IP Core. This IP Core enables designers to easily integrate customizable registers into their projects, allowing for efficient data storage, control, and configuration. Its adaptability and simplicity make it a valuable addition to FPGA and SoC designs, contributing to their flexibility and ease of customization.'}
}

# Import JSON (Optional) -----------------------------------------------------------------------
if args.json:
args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)

rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0")

summary = {
# "DATA WIDTH": args.data_width,
# "DEPTH": 2**(args.addr_width),
"REGISTER SIZE (BYTES)": int(args.data_width/(8))
# "ID WIDTH": args.id_width,
# "AW USER WIDTH": args.aw_user_width,
# "W USER WIDTH": args.w_user_width,
# "B USER WIDTH": args.b_user_width,
# "AR USER WIDTH": args.ar_user_width,
# "R USER WIDTH": args.r_user_width,
# "AW REG TYPE": args.aw_reg_type,
# "W REG TYPE": args.w_reg_type,
# "R REG TYPE": args.r_reg_type,
# "AR REG TYPE": args.ar_reg_type,
# "R REG TYPE": args.r_reg_type
}

# Export JSON Template (Optional) --------------------------------------------------------------
if args.json_template:
rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)

# Create Wrapper -------------------------------------------------------------------------------
platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")
Expand Down
19 changes: 17 additions & 2 deletions rapidsilicon/ip/axil_interconnect/v1_0/axil_interconnect_gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -117,13 +117,28 @@ def main():

args = parser.parse_args()

details = { "IP details": {
'Name' : 'AXI-LITE INTERCONNECT',
'Version' : 'V1_0',
'Interface' : 'AXI-LITE',
'Description' : 'AXI-LITE INTERCONNECT is a AXI-LITE compliant IP Core. It is designed to facilitate efficient communication and data transfer between different AXI Lite (AXIL) bus master and slave peripherals. This IP core acts as a central hub for connecting multiple AXIL bus masters to AXIL bus slaves within the system.'}
}

# Import JSON (Optional) -----------------------------------------------------------------------
if args.json:
args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)

rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0")

summary = {
"NUMBER OF MASTER INTERFACES": args.m_count,
"NUMBER OF SLAVE INTERFACES": args.s_count,
"AXIL DATA PORT WIDTH": args.data_width,
"AXIL ADDR PORT WIDTH": args.addr_width
}

# Export JSON Template (Optional) --------------------------------------------------------------
if args.json_template:
rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)

# Create Wrapper -------------------------------------------------------------------------------
platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")
Expand Down

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