PDP11: 11/70 read-only registers must not return NXM on write

17 777 740 - 17 777 742, read-only error address registers,
and 17 777 764, a read-only System ID register,

and are not handled in the CPU70_wr() routine, which means for these
addresses the routine returns NXM, which then translates to "bus timeout"
(no response to address), and then, as a result, trap to vector 4.

That is incorrect, IMO.

These locations are read-only yet the address gets decoded, and even
though writing does not have any effect, the write routine for these
addresses should return SCPE_OK.

PDP11/pdp11_cpumod.c

@@ -685,6 +685,9 @@ return SCPE_NXM;                                        /* unimplemented */
 t_stat CPU70_wr (int32 data, int32 pa, int32 access)
 {
 switch ((pa >> 1) & 017) {                              /* decode pa<4:1> */
+    case 000:
+    case 001:
+        return SCPE_OK;                                 /* error addr */
 
     case 002:                                           /* MEMERR */
         ODD_SHF (data);
@@ -708,6 +711,9 @@ switch ((pa >> 1) & 017) {                              /* decode pa<4:1> */
     case 011:                                           /* high size */
         return SCPE_OK;
 
+    case 012:                                           /* system ID */
+        return SCPE_OK;
+
     case 013:                                           /* CPUERR */
         CPUERR = 0;
         return SCPE_OK;