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SEL32: Do general code cleanup to remove unused code.
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SEL32: Update Ping and ICMP support code to use correct packet size.
SEL32: Update SetupNet script to support latest Fedora release.
SEL32: Improve disk write speed.
SEL32: Add .tap file reassignent support in sel32_mt.c.
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@AZBevier @pkoning2
AZBevier authored and pkoning2 committed Oct 10, 2023
1 parent 8b9613a commit 25b7933
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Showing 18 changed files with 829 additions and 798 deletions.
32 changes: 14 additions & 18 deletions SEL32/sel32_chan.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,9 +80,7 @@

uint32 channels = MAX_CHAN; /* maximum number of channels */
int subchannels = SUB_CHANS; /* maximum number of subchannel devices */
//int irq_pend = 0; /* pending interrupt flag */

//extern uint32 *M; /* cpu/ipu main memory */
extern uint32 SPAD[]; /* cpu SPAD memory */
extern uint32 CPUSTATUS; /* CPU status word */
extern uint32 INTS[]; /* Interrupt status flags */
Expand Down Expand Up @@ -518,6 +516,7 @@ int32 load_ccw(CHANP *chp, int32 tic_ok)
sim_debug(DEBUG_XIO, &cpu_dev,
"load_ccw @%06x entry chan_status[%02x]=%04x\n",
chp->chan_caw, chan, chp->chan_status);

#ifdef TEST_FOR_IOCL_CHANGE
/* see if iocla or iocd has changed since start */
if (!loading && (chp->chan_info & INFO_SIOCD)) { /* see if 1st IOCD in channel prog */
Expand Down Expand Up @@ -1401,9 +1400,6 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
}
#endif

/* 05122021 cpu halts in diag if this code is enabled */
/* disabling this code allows TE to be echoed at debugger prompt */
#ifndef TEST_FOR_HSDP_PUT_BACK_05122021
/* channel not busy and ready to go, check for any status ready */
/* see if any status ready to post */
if (FIFO_Num(chsa&0x7f00)) {
Expand Down Expand Up @@ -1439,7 +1435,6 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
sim_debug(DEBUG_IRQ, &cpu_dev,
"SIOT chsa %04x Nothing to post FIFO #%1x irq %02x inch %06x chan_icba %06x icb+20 %08x\n",
chsa, FIFO_Num(chsa), inta, incha, chan_icb, RMW(chan_icb+20));
#endif

/* check for a Command or data chain operation in progresss */
if ((chp->chan_byte & BUFF_BUSY) && (chp->chan_byte != BUFF_POST)) {
Expand Down Expand Up @@ -1602,7 +1597,8 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
/* we have an error or user requested interrupt, return status */
sim_debug(DEBUG_EXP, &cpu_dev, "startxio store csw CC2 chan %04x status %08x\n",
chan, chp->chan_status);
/*NOTE*//* if we have an error, we would loop forever if the CC bit was set */
/* NOTE */
/* if we have an error, we would loop forever if the CC bit was set */
/* the only way to stop was to do a kill */
chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* reset chaining bits */
/* DIAG's want CC1 with memory access error */
Expand Down Expand Up @@ -2067,7 +2063,7 @@ t_stat rschnlxio(uint16 lchsa, uint32 *status) { /* reset channel XIO */
}
sim_debug(DEBUG_XIO, &cpu_dev, "RSCHNL return CC1 lchsa %02x chan %02x inta %04x\n",
lchsa, chan, inta);
*status = CC1BIT; /* request accepted, no status, so CC1 TRY THIS */
*status = CC1BIT; /* request accepted, no status, so CC1 */
return SCPE_OK; /* All OK */
}

Expand Down Expand Up @@ -2136,7 +2132,8 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
if ((dptr->flags & DEV_DIS) || ((uptr->flags & UNIT_DIS) &&
((uptr->flags & UNIT_SUBCHAN) == 0))) {
sim_debug(DEBUG_EXP, &cpu_dev,
"HIO chsa %04x device/unit disabled, CC3 returned flags %08x\n", chsa, uptr->flags);
"HIO chsa %04x device/unit disabled, CC3 returned flags %08x\n",
chsa, uptr->flags);
*status = CC3BIT; /* not attached, so error CC3 */
return SCPE_OK; /* not found, CC3 */
}
Expand Down Expand Up @@ -2218,7 +2215,7 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
"HIO END3 chsa %04x cmd %02x ccw_flags %04x status %04x\n",
chsa, chp->ccw_cmd, chp->ccw_flags, *status);

#ifndef GIVE_INT_ON_NOT_BUSY_121420_03082021
/* GIVE_INT_ON_NOT_BUSY */
chp->chan_byte = BUFF_DONE; /* we are done */
sim_debug(DEBUG_EXP, &cpu_dev,
"HIO BUFF_DONE2 chp %p chan_byte %04x\n", chp, chp->chan_byte);
Expand All @@ -2235,7 +2232,6 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
chp->chan_status = 0; /* no status anymore */
chp->ccw_cmd = 0; /* no command anymore */
irq_pend = 1; /* flag to test for int condition */
#endif
return SCPE_OK; /* No CC's all OK */
}

Expand Down Expand Up @@ -2356,7 +2352,8 @@ t_stat grabxio(uint16 lchsa, uint32 *status) { /* grab controller XIO n/u */
if ((dptr->flags & DEV_DIS) || ((uptr->flags & UNIT_DIS) &&
((uptr->flags & UNIT_SUBCHAN) == 0))) {
sim_debug(DEBUG_EXP, &cpu_dev,
"GRIO chsa %04x device/unit disabled, CC3 returned flags %08x\n", chsa, uptr->flags);
"GRIO chsa %04x device/unit disabled, CC3 returned flags %08x\n",
chsa, uptr->flags);
*status = CC3BIT; /* not attached, so error CC3 */
return SCPE_OK; /* not found, CC3 */
}
Expand All @@ -2370,7 +2367,6 @@ t_stat grabxio(uint16 lchsa, uint32 *status) { /* grab controller XIO n/u */
return SCPE_OK; /* CC4 all OK */
}

// NOW ON 05142021 */
/* device does not have stop_io entry, so stop the I/O */
/* check for a Command or data chain operation in progresss */
/* set the return to CC3BIT & CC4BIT causes infinite loop in MPX1X */
Expand Down Expand Up @@ -2416,8 +2412,6 @@ t_stat grabxio(uint16 lchsa, uint32 *status) { /* grab controller XIO n/u */

/* If this is console, debugger wants CC3 & CC4 = 0 */
if (chan == 0x7e) {
/* returning No CC's causes MPX1X to loop forever */
/* so restore returning CC1 */
*status = 0; /* return no CC's */
} else {
/* diags want unsupported transaction for disk */
Expand Down Expand Up @@ -2531,7 +2525,8 @@ t_stat chan_boot(uint16 chsa, DEVICE *dptr) {
UNIT *uptr = find_unit_ptr(chsa); /* find pointer to unit on channel */
CHANP *chp = 0;

sim_debug(DEBUG_EXP, &cpu_dev, "Channel Boot chan/device addr %04x SNS %08x\n", chsa, uptr->u5);
sim_debug(DEBUG_EXP, &cpu_dev,
"Channel Boot chan/device addr %04x SNS %08x\n", chsa, uptr->u5);
fflush(sim_deb);

if (dibp == 0) /* if no channel or device, error */
Expand Down Expand Up @@ -2626,8 +2621,9 @@ uint32 cont_chan(uint16 chsa)
/* we have an error or user requested interrupt, return status */
sim_debug(DEBUG_EXP, &cpu_dev, "cont_chan error, store csw chsa %04x status %08x\n",
chsa, chp->chan_status);
/*NOTE*/ /* if we have an error, we would loop forever if the CC bit was set */
/* the only way to stop was to do a kill */
/* NOTE */
/* if we have an error, we would loop forever if the CC bit was set */
/* the only way to stop was to do a kill of sel32 */
chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* reset chaining bits */
/* DIAG's want CC1 with memory access error */
if (chp->chan_status & STATUS_PCHK) {
Expand Down
36 changes: 5 additions & 31 deletions SEL32/sel32_clk.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,6 @@ int32 rtc_lvl = 0x18; /* rtc interrupt level */

/* clock can be enabled / disabled */
/* default to 60 HZ RTC */
//718UNIT rtc_unit = { UDATA (&rtc_srv, UNIT_IDLE, 0), 16666, UNIT_ADDR(0x7F06)};
UNIT rtc_unit = { UDATA (&rtc_srv, UNIT_CLK, 0), 16666, UNIT_ADDR(0x7F06)};

REG rtc_reg[] = {
Expand Down Expand Up @@ -111,10 +110,6 @@ t_stat rtc_srv (UNIT *uptr)
#endif
/* if clock disabled, do not do interrupts */
if (((rtc_dev.flags & DEV_DIS) == 0) && rtc_pie) {
int lev = rtc_lvl;
sim_debug(DEBUG_CMD, &rtc_dev,
"RT Clock mfp INTS[%02x] %08x SPAD[%02x] %08x\n",
lev, INTS[lev], lev+0x80, SPAD[lev+0x80]);
sim_debug(DEBUG_CMD, &rtc_dev,
"RT Clock int INTS[%02x] %08x SPAD[%02x] %08x\n",
rtc_lvl, INTS[rtc_lvl], rtc_lvl+0x80, SPAD[rtc_lvl+0x80]);
Expand Down Expand Up @@ -142,7 +137,6 @@ t_stat rtc_srv (UNIT *uptr)
"RT Clock int INTS[%02x] %08x SPAD[%02x] %08x\n",
rtc_lvl, INTS[rtc_lvl], rtc_lvl+0x80, SPAD[rtc_lvl+0x80]);
}
// temp = sim_rtcn_calb(rtc_tps, TMR_RTC); /* timer 0 for RTC */
sim_rtcn_calb(rtc_tps, TMR_RTC); /* timer 0 for RTC */
sim_activate_after(uptr, 1000000/rtc_tps); /* reactivate 16666 tics / sec */
return SCPE_OK;
Expand All @@ -161,7 +155,7 @@ void rtc_setup(uint32 ss, uint32 level)
if (ss == 1) { /* starting? */
INTS[level] |= INTS_ENAB; /* make sure enabled */
SPAD[level+0x80] |= SINT_ENAB; /* in spad too */
sim_activate(&rtc_unit, 20); /* start us off */
sim_activate(&rtc_unit, 20); /* start us off, will be ignored if active */
sim_debug(DEBUG_CMD, &rtc_dev,
"RT Clock setup enable int %02x rtc_pie %01x ss %01x\n",
rtc_lvl, rtc_pie, ss);
Expand All @@ -182,7 +176,8 @@ t_stat rtc_reset(DEVICE *dptr)
{
rtc_pie = 0; /* disable pulse */
/* initialize clock calibration */
sim_activate (&rtc_unit, rtc_unit.wait); /* activate unit */
sim_rtcn_init_unit(&rtc_unit, rtc_unit.wait, TMR_RTC);
sim_activate(&rtc_unit, rtc_unit.wait); /* activate unit, ignored for second reset */
return SCPE_OK;
}

Expand Down Expand Up @@ -282,7 +277,6 @@ DEVICE itm_dev = {
NULL, NULL, &itm_reset, /* examine, deposit, reset */
NULL, NULL, NULL, /* boot, attach, detach */
/* dib, dev flags, debug flags, debug */
// NULL, DEV_DEBUG|DEV_DIS|DEV_DISABLE, 0, dev_debug,
NULL, DEV_DEBUG, 0, dev_debug, /* dib, dev flags, debug flags, debug */
NULL, NULL, &itm_help, /* ?, ?, help */
NULL, NULL, &itm_desc, /* ?, ?, description */
Expand All @@ -299,10 +293,9 @@ DEVICE itm_dev = {
t_stat itm_srv (UNIT *uptr)
{
if (itm_pie) { /* interrupt enabled? */
time_t result = time(NULL);
sim_debug(DEBUG_CMD, &itm_dev,
"Intv Timer expired status %08x lev %02x cnt %x @ time %08x\n",
INTS[itm_lvl], itm_lvl, itm_cnt, (uint32)result);
"Intv Timer expired status %08x lev %02x cnt %x\n",
INTS[itm_lvl], itm_lvl, itm_cnt);
if (((INTS[itm_lvl] & INTS_ENAB) || /* make sure enabled */
(SPAD[itm_lvl+0x80] & SINT_ENAB)) && /* in spad too */
(((INTS[itm_lvl] & INTS_ACT) == 0) || /* and not active */
Expand Down Expand Up @@ -421,17 +414,7 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
sim_activate_after_abs_d(&itm_unit, ((double)cnt*1000000)/rtc_tps);
else {
/* use interval timer freq */
#ifdef MAYBE_CHANGE_FOR_MPX3X
/* tsm does not run if fake time cnt is used */
/// if (cnt == 0)
/// cnt = 0x52f0;
/* this fixes an extra interrupt being generated on context switch */
/* the value is load for the new task anyway */
/* need to verify that UTX likes it too */
/*4MPX3X*/ sim_activate_after_abs_d(&itm_unit, ((double)(cnt+1)*itm_tick_size_x_100)/100.0);
#else
sim_activate_after_abs_d(&itm_unit, ((double)cnt*itm_tick_size_x_100)/100.0);
#endif
}
itm_run = 1; /* set timer running */
}
Expand Down Expand Up @@ -607,7 +590,6 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
/* get simulated negative start time in counts */
temp = temp - itm_strt; /* make into a negative number */
}
//extra sim_cancel (&itm_unit); /* cancel timer */
}
sim_debug(DEBUG_CMD, &itm_dev,
"Intv 0x%02x temp value %08x (%08d)\n", cmd, temp, temp);
Expand Down Expand Up @@ -657,18 +639,10 @@ void itm_setup(uint32 ss, uint32 level)
itm_cnt = 0; /* no count reset value */
sim_cancel (&itm_unit); /* not running yet */
if (ss == 1) { /* starting? */
#ifdef NOT_HERE_112422
INTS[level] |= INTS_ENAB; /* make sure enabled */
SPAD[level+0x80] |= SINT_ENAB; /* in spad too */
#endif
sim_debug(DEBUG_CMD, &itm_dev,
"Intv Timer setup enable int %02x value %08x itm_pie %01x ss %01x\n",
itm_lvl, itm_cnt, itm_pie, ss);
} else {
#ifdef NOT_HERE_112422
INTS[level] &= ~INTS_ENAB; /* make sure disabled */
SPAD[level+0x80] &= ~SINT_ENAB; /* in spad too */
#endif
sim_debug(DEBUG_CMD, &itm_dev,
"Intv Timer setup disable int %02x value %08x itm_pie %01x ss %01x\n",
itm_lvl, itm_cnt, itm_pie, ss);
Expand Down
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