Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[rtl] fix a typo. #2212

Merged
merged 1 commit into from
Aug 28, 2024
Merged

[rtl] fix a typo. #2212

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion rtl/ibex_core.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1678,7 +1678,7 @@ module ibex_core import ibex_pkg::*; #(
end


// Memory adddress/write data available first cycle of ld/st instruction from register read
// Memory address/write data available first cycle of ld/st instruction from register read
always_comb begin
if (instr_first_cycle_id) begin
rvfi_mem_addr_d = alu_adder_result_ex;
Expand Down
Loading