add RISC-V debug module to FPGA example #1218
Conversation
Import a copy of ./hw/vendor/pulp_riscv_dbg from opentitan project, and place it in ./vendor/.
Overhaul top_artya7.sv to both instantiate a debug module and provide bus arbitration between all three bus hosts (Ibex instr, Ibex data, and the debug module). A defacto standard from SiFive on JTAG pinouts exists for Arty boards; adapt the existing pin constraints to use this standard.
Set the ibex_core parameters 'DbgTriggerEn' and 'DbgHwBreakNum' for two hardware breakpoints when DBG is enabled. Enabling this in the Ibex core is strongly desirable to present a good debug experience. Moreover, some RISC-V debug tools assume that breakpoints exist on the target, so failure to have this in the example only causes a frustrated user.
|
Hi @majbthrd thank you for this contribution. Sorry for taking our time in responding. We are interested in having a good debug module example in a basic Ibex system. We're just having some internal discussion as to where it should live. We'd like the Ibex repository to remain focused on Ibex itself so as examples and systems get more complex we'll want a different place for them to be. What you've done looks like a great starting point for our more complete example system. It will take us a while longer to work out what we're doing here but rest assured this has not been discarded or forgotten. |
|
Thanks for the message. I agree that makes sense to decouple the core Ibex RTL from other code. FYI: previously, the SEGGER J-Link debug pod was not compatible with the pulp-platform/riscv-dbg module. It would be unrealistic to expect that SEGGER should devise their own Ibex implementation from scratch for testing, but by providing them with pre-compiled bitstreams for the Arty FPGA board (using this PR), they were able to test it locally, the problem was identified, and V6.94c+ (05 Feb 2021) does now work with the target (Ibex + riscv-dbg). |
I thought the FPGA Ibex offering might be enhanced by including a ready-to-use (but with the flexibility to opt-out, if desired, at synthesis time) example RISC-V debug implementation.
My goal was as much design re-use as possible. SiFive already has a defacto standard for JTAG pinouts on the Arty boards, so I followed that. The RISC-V debug module is a direct copy of the OpenTitan variant of the pulp-platform/riscv-dbg module.
The top level of the debug was customized to suit the FPGA example (the OpenTitan variant has a nicer integration of JTAG signals and IDCODE implementation, but no TileLink bus is used on the Ibex project), and top_artya7.sv was overhauled to instantiate the top-level debug module and provide bus arbitration between all three bus hosts.