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WIP Logic gates #4

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WIP Logic gates #4

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Commits on Jul 27, 2021

  1. Add basic logic gates.

    @yashton
    yashton committed Jul 27, 2021
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  2. Fix schematic layout

    @yashton
    yashton committed Jul 27, 2021
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  3. Add TSPC flip-flop

    @yashton
    yashton committed Jul 27, 2021
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  4. Rename dash to underscore in symbols.

    @yashton
    yashton committed Jul 27, 2021
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Commits on Jul 29, 2021

  1. Added layout for standard cells

    @HugoM41tr3
    HugoM41tr3 committed Jul 29, 2021
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Commits on Aug 5, 2021

  1. Add minority3 gate.

    @yashton
    yashton committed Aug 5, 2021
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Commits on Aug 27, 2021

  1. Add two to four demux.

    @yashton
    yashton committed Aug 27, 2021
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Commits on Aug 30, 2021

  1. Add layouts for inverter, xor

    @yashton
    yashton committed Aug 30, 2021
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Commits on Sep 8, 2021

  1. Add layout sketches and a number of gates.

    @yashton
    yashton committed Sep 8, 2021
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Commits on Sep 16, 2021

  1. [TIGFET10nm] Layout of the new 15nm TIGFET 

    - TILEG1
- TILEG2
- XOR3
- MAJ & MAJBAR
- INV1 & INV2
- NOR2
- FULL ADDER OPTIMIZED (FAO)
- PCELLS SP15CP15
- TILE No Connections
    @leaenginger
    leaenginger committed Sep 16, 2021
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Commits on Sep 25, 2021

  1. Cleanup

    @yashton
    yashton committed Sep 25, 2021
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  2. Merge remote-tracking branch 'origin/layout-tigfet15nm' into logic-gates

    @yashton
    yashton committed Sep 25, 2021
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Commits on Oct 4, 2021

  1. Update drc to match pdf numbers.

    @yashton
    yashton committed Oct 4, 2021
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