fix: reg bitwidth assignment

litneet64 · May 31, 2024 · 6bfcd1d · 6bfcd1d
1 parent 52a05dd
commit 6bfcd1d
Showing 1 changed file with 1 addition and 3 deletions.
diff --git a/src/puf_bit.v b/src/puf_bit.v
@@ -7,16 +7,14 @@ module puf_bit(
 
     localparam n_ro = 32;
     localparam n_half = n_ro / 2;
-    parameter BITWIDTH = n_ro;
 
     wire[n_ro-1:0] ro_out;
     reg[n_ro-1:0] inter_en;
 
     wire mux_out_1, mux_out_2;
     wire ctr_out_1, ctr_out_2;
 
-
-    assign inter_en[n_ro-1:0] = BITWIDTH'd1;
+    assign inter_en = (en) ? n_ro'b1 : n_ro'b0;
 
     ring_osc ro_array_1[n_half-1:0] (inter_en[n_half-1:0], ro_out[n_half-1:0]);
     ring_osc ro_array_2[n_half-1:0] (inter_en[n_ro-1:n_half], ro_out[n_ro-1:n_half]);