fix: extra newlines and const bitwidth

litneet64 · May 31, 2024 · 52a05dd · 52a05dd
1 parent 84fae87
commit 52a05dd
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Showing 5 changed files with 11 additions and 6 deletions.
diff --git a/src/arbiter.v b/src/arbiter.v
@@ -1,3 +1,4 @@
+
 module arbiter (
     input wire out_1, out_2, clk, rst,
     output wire resp, finish
@@ -26,4 +27,4 @@ module arbiter (
 
     end
 
-endmodule
+endmodule
diff --git a/src/counter.v b/src/counter.v
@@ -1,3 +1,4 @@
+
 module counter(
     input wire in, clk, rst,
     output wire out
@@ -24,4 +25,4 @@ module counter(
     end
 
 
-endmodule
+endmodule
diff --git a/src/mux_16.v b/src/mux_16.v
@@ -1,3 +1,4 @@
+
 module mux_16 (
     input wire[15:0] ro,
     input wire[3:0] chall,
@@ -29,4 +30,4 @@ module mux_16 (
     end
 
 
-endmodule
+endmodule
diff --git a/src/puf_bit.v b/src/puf_bit.v
@@ -1,3 +1,4 @@
+
 module puf_bit(
     input wire[7:0] chall,
     input wire clk, rst, en,
@@ -6,14 +7,16 @@ module puf_bit(
 
     localparam n_ro = 32;
     localparam n_half = n_ro / 2;
+    parameter BITWIDTH = n_ro;
 
     wire[n_ro-1:0] ro_out;
     reg[n_ro-1:0] inter_en;
 
     wire mux_out_1, mux_out_2;
     wire ctr_out_1, ctr_out_2;
 
-    assign inter_en[n_ro-1:0] = n_ro'd1;
+
+    assign inter_en[n_ro-1:0] = BITWIDTH'd1;
 
     ring_osc ro_array_1[n_half-1:0] (inter_en[n_half-1:0], ro_out[n_half-1:0]);
     ring_osc ro_array_2[n_half-1:0] (inter_en[n_ro-1:n_half], ro_out[n_ro-1:n_half]);
@@ -26,4 +29,4 @@ module puf_bit(
 
     arbiter race_arb(cnt_out_1, cnt_out_2, clk, rst, resp, finish);
 
-endmodule
+endmodule
diff --git a/src/ring_osc.v b/src/ring_osc.v
@@ -19,4 +19,3 @@ module ring_osc(
     assign out = inter_wire[num_inv];
 
 endmodule 
-
Original file line number	Diff line number	Diff line change
Expand Up		@@ -19,4 +19,3 @@ module ring_osc(
		assign out = inter_wire[num_inv];

		endmodule