Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Update RISC-V toolchain #771

Merged
merged 4 commits into from
Dec 10, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion .github/workflows/benchmark.yml
Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ jobs:
(github.event.action == 'labeled' && github.event.label.name == 'benchmark')
)
)
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.12.07
steps:
- name: Checkout
uses: actions/checkout@v4
Expand Down
4 changes: 2 additions & 2 deletions .github/workflows/main.yml
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ jobs:
build-riscof-tests:
name: Build regression tests (riscv-arch-test)
runs-on: ubuntu-latest
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.12.07
timeout-minutes: 10
env:
PYENV_ROOT: "/root/.pyenv"
Expand Down Expand Up @@ -200,7 +200,7 @@ jobs:
build-regression-tests:
name: Build regression tests (riscv-tests)
runs-on: ubuntu-latest
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.03.12
container: ghcr.io/kuznia-rdzeni/riscv-toolchain:2024.12.07
timeout-minutes: 10
steps:
- name: Checkout
Expand Down
14 changes: 7 additions & 7 deletions docker/riscv-toolchain.Dockerfile
Original file line number Diff line number Diff line change
@@ -1,25 +1,25 @@
FROM ubuntu:23.04
FROM ubuntu:24.04

RUN apt-get update && \
DEBIAN_FRONTEND=noninteractive \
apt-get install -y --no-install-recommends \
autoconf automake autotools-dev curl python3.11 python3.11-venv python3-pip bc lsb-release \
autoconf automake autotools-dev curl python3 python3-venv python3-pip bc lsb-release \
libmpc-dev libmpfr-dev libgmp-dev gawk build-essential \
bison flex texinfo gperf libtool patchutils zlib1g-dev device-tree-compiler \
libexpat-dev ninja-build git ca-certificates python-is-python3 \
libssl-dev libbz2-dev libreadline-dev libsqlite3-dev libncursesw5-dev xz-utils tk-dev libxml2-dev libxmlsec1-dev libffi-dev liblzma-dev && \
rm -rf /var/lib/apt/lists/*

RUN git clone --shallow-since=2023.05.01 https://github.com/riscv/riscv-gnu-toolchain && \
RUN git clone --shallow-since=2024.11.20 https://github.com/riscv-collab/riscv-gnu-toolchain && \
cd riscv-gnu-toolchain && \
git checkout 2023.12.10 && \
./configure --with-multilib-generator="rv32i-ilp32--a*zifence*zicsr;rv32im-ilp32--a*zifence*zicsr;rv32ic-ilp32--a*zifence*zicsr;rv32imc-ilp32--a*zifence*zicsr;rv32imfc-ilp32f--a*zifence;rv32imc_zba_zbb_zbc_zbs-ilp32--a*zifence*zicsr" && \
git checkout 2024.11.22 && \
./configure --with-multilib-generator="rv32i-ilp32--a*zifence*zicsr;rv32im-ilp32--a*zifence*zicsr;rv32ic-ilp32--a*zifence*zicsr;rv32imc-ilp32--a*zifence*zicsr;rv32imfc-ilp32f--a*zifence;rv32imc_zba_zbb_zbc_zbs_zicond-ilp32--a*zifence*zicsr" && \
make -j$(nproc) && \
cd / && rm -rf riscv-gnu-toolchain

RUN git clone --shallow-since=2023.10.01 https://github.com/riscv-software-src/riscv-isa-sim.git spike && \
RUN git clone --shallow-since=2024.10.01 https://github.com/riscv-software-src/riscv-isa-sim.git spike && \
cd spike && \
git checkout eeef09ebb894c3bb7e42b7b47aae98792b8eef79 && \
git checkout 7812eabb441eaf2067d07636a382eca622e48814 && \
mkdir build/ install/ && \
cd build/ && \
../configure --prefix=/spike/install/ && \
Expand Down
4 changes: 2 additions & 2 deletions test/external/embench/board_config/coreblocks-sim/board.cfg
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
cc = 'riscv64-unknown-elf-gcc'
cflags = (['-c', '-fdata-sections', '-march=rv32imc_zba_zbb_zbc_zbs_zicsr', '-mabi=ilp32'])
ldflags = (['-Wl,-gc-sections', '-march=rv32imc_zba_zbb_zbc_zbs_zicsr', '-mabi=ilp32', '-nostartfiles', '-T../../../common/link.ld'])
cflags = (['-c', '-fdata-sections', '-march=rv32imc_zba_zbb_zbc_zbs_zicsr_zicond', '-mabi=ilp32'])
ldflags = (['-Wl,-gc-sections', '-march=rv32imc_zba_zbb_zbc_zbs_zicsr_zicond', '-mabi=ilp32', '-nostartfiles', '-T../../../common/link.ld'])
user_libs = (['-lm'])
cpu_mhz = 0.01
2 changes: 1 addition & 1 deletion test/external/riscof/riscv-arch-test
Submodule riscv-arch-test updated 1748 files
Loading