Update RISC-V toolchain

[tilk]

This PR updates the RISC-V toolchain used in the CI builds. This includes updated GCC which can take advantage of the zicond extension. The riscv-arch-test dependency also needed to be updated because of a build error.

Benchmarks show some IPC improvements on crc32 , minver and ud , minimal IPC improvement on slre and statemate, and a small decrease on nettle-sha256.

Fixes #748.

[github-actions]

Benchmarks summary

Performance benchmarks

aha-mont64	crc32	minver	nettle-sha256	nsichneu	slre	statemate	ud
0.417	0.525	0.37	0.631	0.359	0.291	0.328	0.44

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
15699	4263	1490	1452	54

Synthesis benchmarks (full)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
22103	6878	1820	1504	43

[github-actions]

Benchmarks summary

Performance benchmarks

aha-mont64	crc32	minver	nettle-sha256	nsichneu	slre	statemate	ud
▼ 0.417 (-0.000)	▲ 0.525 (+0.013)	▲ 0.370 (+0.033)	▼ 0.631 (-0.024)	▼ 0.359 (-0.001)	▲ 0.291 (+0.001)	▲ 0.328 (+0.002)	▲ 0.440 (+0.008)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▼ 14204 (-39)	4398 (0)	▼ 1424 (-32)	1164 (0)	▼ 51 (-2)

Synthesis benchmarks (full)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▼ 22120 (-1355)	7013 (0)	1818 (0)	1216 (0)	▲ 45 (+4)