LiteX support changes

[piotro888]

Misc changes to keep up with LiteX/Zephyr developement:

1. Export interrupts input to Core interface
2. Add M extension to basic configuration. As full shifted very far from basic, it makes sense to me (and default usage).
3. Add some default MMIO region, same as used in default coreblocks LiteX configuration

I can split it if necessary

[piotro888]

Change of basic configuration would shift benchmarks graphs, but I think it needs to by done sometime anyway.

[github-actions]

Benchmarks summary

Performance benchmarks

aha-mont64	crc32	minver	nettle-sha256	nsichneu	slre	statemate	ud
0.417 (0.000)	0.513 (0.000)	0.337 (0.000)	0.655 (0.000)	0.361 (0.000)	0.290 (0.000)	0.326 (0.000)	0.431 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▲ 17044 (+2780)	▲ 6696 (+653)	▲ 1460 (+626)	▲ 1196 (+128)	▼ 54 (-3)

Synthesis benchmarks (full)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▼ 24004 (-872)	▲ 9314 (+16)	▲ 1822 (+32)	1248 (0)	▲ 45 (+2)

[github-actions]

Benchmarks summary

Performance benchmarks

aha-mont64	crc32	minver	nettle-sha256	nsichneu	slre	statemate	ud
0.417 (0.000)	0.513 (0.000)	0.337 (0.000)	0.655 (0.000)	0.361 (0.000)	0.290 (0.000)	0.326 (0.000)	0.431 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▲ 17808 (+3544)	▲ 6696 (+653)	▲ 1460 (+626)	▲ 1196 (+128)	▼ 54 (-3)

Synthesis benchmarks (full)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▼ 24646 (-230)	▲ 9314 (+16)	▲ 1822 (+32)	1248 (0)	▼ 42 (-1)