LiteX support changes (#756)

kuznia-rdzeni · Nov 25, 2024 · 5e0e7d6 · 5e0e7d6
1 parent 2abd9e9
commit 5e0e7d6
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Showing 4 changed files with 27 additions and 11 deletions.
diff --git a/coreblocks/core.py b/coreblocks/core.py
@@ -1,11 +1,11 @@
 from amaranth import *
-from amaranth.lib.wiring import Component, flipped, connect, Out
+from amaranth.lib.wiring import Component, flipped, connect, In, Out
 from transactron.utils.amaranth_ext.elaboratables import ModuleConnector
 
 from transactron.utils.dependencies import DependencyContext
 from coreblocks.priv.traps.instr_counter import CoreInstructionCounter
 from coreblocks.func_blocks.interface.func_blocks_unifier import FuncBlocksUnifier
-from coreblocks.priv.traps.interrupt_controller import InternalInterruptController
+from coreblocks.priv.traps.interrupt_controller import ISA_RESERVED_INTERRUPTS, InternalInterruptController
 from transactron.core import Transaction, TModule
 from transactron.lib import ConnectTrans, MethodProduct
 from coreblocks.interface.layouts import *
@@ -35,12 +35,14 @@
 class Core(Component):
     wb_instr: WishboneInterface
     wb_data: WishboneInterface
+    interrupts: Signal
 
     def __init__(self, *, gen_params: GenParams):
         super().__init__(
             {
                 "wb_instr": Out(WishboneSignature(gen_params.wb_params)),
                 "wb_data": Out(WishboneSignature(gen_params.wb_params)),
+                "interrupts": In(ISA_RESERVED_INTERRUPTS + gen_params.interrupt_custom_count),
             }
         )
 
@@ -115,6 +117,8 @@ def elaborate(self, platform):
 
         m.submodules.csr_generic = self.csr_generic
         m.submodules.interrupt_controller = self.interrupt_controller
+        m.d.comb += self.interrupt_controller.internal_report_level.eq(self.interrupts[0:16])
+        m.d.comb += self.interrupt_controller.custom_report.eq(self.interrupts[16:])
 
         m.submodules.core_counter = core_counter = CoreInstructionCounter(self.gen_params)
 

diff --git a/coreblocks/params/configurations.py b/coreblocks/params/configurations.py
@@ -32,6 +32,13 @@
         [ALUComponent(), ShiftUnitComponent(), JumpComponent(), ExceptionUnitComponent(), PrivilegedUnitComponent()],
         rs_entries=4,
     ),
+    RSBlockComponent(
+        [
+            MulComponent(mul_unit_type=MulType.SEQUENCE_MUL),
+            DivComponent(),
+        ],
+        rs_entries=2,
+    ),
     RSBlockComponent([LSUComponent()], rs_entries=2, rs_type=FifoRS),
     CSRBlockComponent(),
 )
@@ -127,7 +134,7 @@ def __post_init__(self):
 
     instr_buffer_size: int = 4
 
-    interrupt_custom_count: int = 0
+    interrupt_custom_count: int = 16
     interrupt_custom_edge_trig_mask: int = 0
 
     user_mode: bool = True
@@ -139,7 +146,9 @@ def __post_init__(self):
     _implied_extensions: Extension = Extension(0)
     _generate_test_hardware: bool = False
 
-    pma: list[PMARegion] = field(default_factory=list)
+    pma: list[PMARegion] = field(
+        default_factory=lambda: [PMARegion(0xE0000000, 0xFFFFFFFF, mmio=True)]
+    )  # default I/O region used in LiteX coreblocks
 
 
 class CoreConfiguration(_CoreConfigurationDataClass):

diff --git a/test/params/test_configurations.py b/test/params/test_configurations.py
@@ -18,9 +18,9 @@ class ISAStrTest:
     TEST_CASES = [
         ISAStrTest(
             basic_core_config,
-            "rv32izicsr_zifencei_xintmachinemode",
-            "rv32izicsr_zifencei_xintmachinemode",
-            "rv32izicsr_zifencei_xintmachinemode",
+            "rv32imzicsr_zifencei_xintmachinemode",
+            "rv32imzicsr_zifencei_xintmachinemode",
+            "rv32imzicsr_zifencei_xintmachinemode",
         ),
         ISAStrTest(
             full_core_config,

diff --git a/test/test_core.py b/test/test_core.py
@@ -15,6 +15,7 @@
 from coreblocks.params.instr import *
 from coreblocks.params.configurations import *
 from coreblocks.peripherals.wishbone import WishboneMemorySlave
+from coreblocks.priv.traps.interrupt_controller import ISA_RESERVED_INTERRUPTS
 
 import random
 import subprocess
@@ -44,10 +45,12 @@ def elaborate(self, platform):
 
         self.core = Core(gen_params=self.gen_params)
 
-        self.interrupt_level = Signal()
-        self.interrupt_edge = Signal()
-
-        m.d.comb += self.core.interrupt_controller.custom_report.eq(Cat(self.interrupt_edge, self.interrupt_level))
+        if self.gen_params.interrupt_custom_count == 2:
+            self.interrupt_level = Signal()
+            self.interrupt_edge = Signal()
+            m.d.comb += self.core.interrupts.eq(
+                Cat(self.interrupt_edge, self.interrupt_level) << ISA_RESERVED_INTERRUPTS
+            )
 
         m.submodules.wb_mem_slave = self.wb_mem_slave
         m.submodules.wb_mem_slave_data = self.wb_mem_slave_data